Integrated Intel
®
High Definition Audio Controller Registers
726 Datasheet
1
Stream Run (RUN) — R/W.
0 = DMA engine associated with this input stream will be disabled. The hardware will
report a 0 in this bit when the DMA engine is actually stopped. Software must read
a 0 from this bit before modifying related control registers or restarting the DMA
engine.
1 = DMA engine associated with this input stream will be enabled to transfer data from
the FIFO to the main memory. The SSYNC bit must also be cleared in order for the
DMA engine to run. For output streams, the cadence generator is reset whenever
the RUN bit is set.
0
Stream Reset (SRST) — R/W.
0 = Writing a 0 causes the corresponding stream to exit reset. When the stream
hardware is ready to begin operation, it will report a 0 in this bit. Software must
read a 0 from this bit before accessing any of the stream registers.
1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor
registers (except the SRST bit itself) and FIFOs for the corresponding stream are
reset. After the stream hardware has completed sequencing into the reset state, it
will report a 1 in this bit. Software must read a 1 from this bit to verify that the
stream is in reset. The RUN bit must be cleared before SRST is asserted.
Bit Description
To Next Page
Loading...