PCI Express* Configuration Registers
776 Datasheet
19.1.29 LCTL—Link Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 50h–51h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:10 Reserved
9
Hardware Autonomous Width Disable – RO. Hardware never attempts to change
the link width except when attempting to correct unreliable Link operation.
8Reserved
7
Extended Synch (ES) — R/W.
0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from
L1 prior to entering L0.
6
Common Clock Configuration (CCC) — R/W.
0 = The PCH and device are not using a common reference clock.
1 = The PCH and device are operating with a distributed common reference clock.
5
Retrain Link (RL) — R/W.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5/F6/F7:52, bit 11) to check the
status of training.
NOTE: It is permitted to write 1b to this bit while simultaneously writing modified
values to other fields in this register. If the LTSSM is not already in Recovery or
Configuration, the resulting Link training must use the modified values. If the
LTSSM is already in Recovery or Configuration, the modified values are not
required to affect the Link training that is already in progress.
4
Link Disable (LD) — R/W.
0 = Link enabled.
1 = The root port will disable the link.
3
Read Completion Boundary Control (RCBC) — RO. Indicates the read completion
boundary is 64 bytes.
2Reserved
1:0
Active State Link PM Control (APMC) — R/W. Indicates whether the root port should
enter L0s or L1 or both.
00 = Disabled
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled
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