Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 787

Datasheet 787
PCI Express* Configuration Registers
19.1.48 MPC2—Miscellaneous Port Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: D4h–D7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:6 Reserved
5
PCIe 2.0 Compliance Mode Enable (PCME) — R/W.
0 = Compliance mode is disabled.
1 = With proper termination PCH PCIe ports will transmit compliance pattern.
NOTE: This bit should only be set when testing for electrical compliance specified
by the PCI SIG. This bit should not be set during normal system operations.
4
ASPM Control Override Enable (ASPMCOEN) — R/W.
1 = DMI will use the values in the ASPM Control Override registers
0 = DMI will use the ASPM Registers in the Link Control register.
NOTES:This register allows BIOS to control the DMI ASPM settings instead of the
OS.
3:2
ASPM Control Override (ASPMO) — R/W. Provides BIOS control of whether DMI
should enter L0s or L1 or both.
00 = Disabled
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled.
1
EOI Forwarding Disable (EOIFD) — R/W. When set, EOI messages are not
claimed on the backbone by this port an will not be forwarded across the PCIe link.
0 = Broadcast EOI messages that are sent on the backbone are claimed by this
port and forwarded across the PCIe link.
1 = Broadcast EOI messages are not claimed on the backbone by this port and will
not be forwarded across the PCIe Link.
0
L1 Completion Timeout Mode (LICTM) — R/W.
0 = PCI Express Specification Compliant. Completion timeout is disabled during
software initiated L1, and enabled during ASPM initiate L1.
1 = Completion timeout is enabled during L1, regardless of how L1 entry was
initiated.