High Precision Event Timer Registers
800 Datasheet
NOTES:
1. Reads to reserved registers or bits will return a value of 0.
2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision
Event Timers. If attempted, the lock is not honored, which means potential deadlock
conditions may occur.
130–13Fh — Reserved — —
140–147h TIM2_CONF Timer 2 Configuration and Capabilities N/A R/W, RO
148–14Fh TIM2_COMP Timer 2 Comparator Value N/A R/W
150–15Fh — Reserved — —
160–167h TIM3_CONG Timer 3 Configuration and Capabilities N/A R/W, RO
168–16Fh TIM3_COMP Timer 3 Comparator Value N/A R/W
180–187h TIM4_CONG Timer 4 Configuration and Capabilities N/A R/W, RO
188–18Fh TIM4_COMP Timer 4 Comparator Value N/A R/W
190–19Fh — Reserved — —
1A0–1A7h TIM5_CONG Timer 5 Configuration and Capabilities N/A R/W, RO
1A8–1AFh TIM5_COMP Timer 5 Comparator Value N/A R/W
1B0–1BFh — Reserved — —
1C0–1C7h TIM6_CONG Timer 6 Configuration and Capabilities N/A R/W, RO
1C8–1CFh TIM6_COMP Timer 6 Comparator Value N/A R/W
1D0–1DFh — Reserved — —
1E0–1E7h TIM7_CONG Timer 7 Configuration and Capabilities N/A R/W, RO
1E8–1EFh TIM7_COMP Timer 7 Comparator Value N/A R/W
1F0–19Fh — Reserved — —
200–3FFh — Reserved — —
Table 20-1. Memory-Mapped Registers (Sheet 2 of 2)
Offset Mnemonic Register Default Type
To Next Page
