Datasheet 827
Serial Peripheral Interface (SPI)
21.1.25 FDOD—Flash Descriptor Observability Data Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + B4h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register that can be used to observe the contents of the Flash Descriptor that is
stored in the PCH Flash Controller.
21.1.26 AFC—Additional Flash Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + C0hAttribute: RO, R/W
Default Value: 00000000hSize: 32 bits.
21.1.27 LVSCC— Host Lower Vendor Specific Component
Capabilities Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + C4h Attribute: RO, R/WL
Default Value: 00000000h Size: 32 bits
Note: All attributes described in LVSCC must apply to all flash space below the FPBA, even if
it spans between two separate flash parts. This register is only applicable when SPI
device is in descriptor mode.
Bit Description
31:0
Flash Descriptor Section Data (FDSD) — RO. Returns the DW of data to observe as
selected in the Flash Descriptor Observability Control.
Bit Description
31:3 Reserved.
2:1
Flash Controller Interface Dynamic Clock Gating Enable — R/W.
0 = Flash Controller Interface Dynamic Clock Gating is Disabled
1 = Flash Controller Interface Dynamic Clock Gating is Enabled
Other configurations are Reserved.
0
Flash Controller Core Dynamic Clock Gating Enable — R/W.
0 = Flash Controller Core Dynamic Clock Gating is Disabled
1 = Flash Controller Core Dynamic Clock Gating is Enabled
Bit Description
31:24 Reserved.
23
Vendor Component Lock (LVCL) — R/W. This register locks itself when set.
0 = The lock bit is not set
1 = The Vendor Component Lock bit is set.
NOTE: This bit applies to both UVSCC and LVSCC registers.
22:16 Reserved
15:8
Lower Erase Opcode (LEO)— R/W. This register is programmed with the Flash erase
instruction opcode required by the vendor’s Flash component.
This register is locked by the Vendor Component Lock (LVCL) bit.
7:5 Reserved
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