Datasheet 831
Serial Peripheral Interface (SPI)
21.1.30 SRDL — Soft Reset Data Lock
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + F0h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
21.1.31 SRDC — Soft Reset Data Control
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + F4h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
21.1.32 SRD — Soft Reset Data
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + F8h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
Bit Description
31:1 Reserved.
0
Set_Stap Lock (SSL) — R/WL.
0 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers
are writeable.
1 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers
are locked.
NOTE: That this bit is reset to ‘0’ on CF9h resets.
Bit Description
31:1 Reserved.
0
Soft Reset Data Select (SRDS) — R/WL.
0 = The Set_Strap data sends the default processor configuration data.
1 = The Set_Strap message bits come from the Set_Strap Msg Data register.
NOTES:
1. This bit is reset by the RSMRST# or when the Resume well loses power.
2. This bit is locked by the SSL bit (SPIBAR+F0h:bit 0).
Bit Description
31:14 Reserved.
13:0
Set_Stap Data (SSD) — R/WL.
NOTES:
1. These bits are reset by the RSMRST#, or when the Resume well loses power.
2. These bits are locked by the SSL bit (SPIBAR+F0h:bit 0).
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