Datasheet 841
Serial Peripheral Interface (SPI)
21.4.13 SSFS—Software Sequencing Flash Status Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 90h Attribute: RO, R/WC
Default Value: 00h Size: 8 bits
Note: The Software Sequencing control and status registers are reserved if the hardware
sequencing control and status registers are used.
Bit Description
7:5 Reserved
4
Access Error Log (AEL) — RO. This bit reflects the value of the Hardware Sequencing
Status AEL register.
3
Flash Cycle Error (FCERR) — R/WC. Hardware sets this bit to 1 when a programmed
access is blocked from running on the SPI interface due to one of the protection policies
or when any of the programmed cycle registers is written while a programmed access is
already in progress. This bit remains asserted until cleared by software writing a 1 or
hardware reset due to a global reset or host partition reset in an Intel
®
ME enabled
system.
2
Cycle Done Status — R/WC. The PCH sets this bit to 1 when the SPI Cycle completes
(that is, SCIP bit is 0) after software sets the GO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
reset in an Intel
®
ME enabled system. When this bit is set and the SPI SMI# Enable bit
is set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
1 Reserved
0
SPI Cycle In Progress (SCIP) — RO. Hardware sets this bit when software sets the
SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes
on the SPI interface. Hardware automatically sets and clears this bit so that software
can determine when read data is valid and/or when it is safe to begin programming the
next command. Software must only program the next command when this bit is 0.
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