Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 852

Thermal Sensor Registers (D31:F6)
852 Datasheet
22.1.21 PID—PCI Power Management Capability ID
Address Offset: 50h–51h Attribute: RO
Default Value: 0001h Size: 16 bits
22.1.22 PC—Power Management Capabilities
Address Offset: 52h–53h Attribute: RO
Default Value: 0023h Size: 16 bits
Bit Description
15:8
Next Capability (NEXT) — RO. Indicates that this is the last capability structure in
the list.
7:0 Cap ID (CAP) — RO. Indicates that this pointer is a PCI power management capability
Bit Description
15:11 PME_Support — RO. Indicates PME# is not supported
10 D2_Support — RO. The D2 state is not supported.
9 D1_Support — RO. The D1 state is not supported.
8:6
Aux_Current — RO. PME# from D3COLD state is not supported, therefore this field is
000b.
5
Device Specific Initialization (DSI) — RO. Indicates that device-specific
initialization is required.
4 Reserved
3 PME Clock (PMEC) — RO. Does not apply. Hardwired to 0.
2:0
Version (VS) — RO. Indicates support for Revision 1.2 of the PCI Power Management
Specification.