Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
914 Datasheet
23.7 IDE BAR1
23.7.1 IDDCR—IDE Device Control Register (IDER—D22:F2)
Address Offset: 2h Attribute: WO
Default Value: 00h Size: 8 bits
This register implements the Device Control register of the Control block of the IDE
function. This register is Write only by the Host.
When the HOST reads to the same address it reads the Alternate Status register.
23.7.2 IDASR—IDE Alternate status Register (IDER—D22:F2)
Address Offset: 2h Attribute: RO
Default Value: 00h Size: 8 bits
This register implements the Alternate Status register of the Control block of the IDE
function. This register is a mirror register to the status register in the command block.
Reading this register by the HOST does not clear the IDE interrupt of the DEV selected
device
Host read of this register when DEV=0 (Master), Host gets the mirrored data of
IDESD0R register.
Host read of this register when DEV=1 (Slave), host gets the mirrored data of IDESD1R
register.
Address
Offset
Register
Symbol
Register Name
Default
Value
Attribute
2h IDDCR IDE Device Control Register 00h RO, WO
2h IDASR IDE Alternate status Register 00h RO
Bit Description
7:3 Reserved
2
Software reset (S_RST) — WO. When this bit is set by the Host, it forces a reset
to the device.
1
Host interrupt Disable (nIEN) — WO. When set, this bit disables hardware from
sending interrupt to the Host.
0 Reserved
Bit Description
7:0
IDE Alternate Status Register (IDEASR)— RO. This field mirrors the value of the
DEV0/ DEV1 status register, depending on the state of the DEV bit on Host reads.
To Next Page
Loading...