Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 934

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
934 Datasheet
23.10.10 KTLSR—KT Line Status Register (KT—D23:F3)
Address Offset: 05h Attribute: WO
Default Value: 00h Size: 8 bits
This register provides status information of the data transfer to the Host. Error
indication, etc. are provided by the HW/FW to the host using this register.
Bit Description
7
RX FIFO Error (RXFER)— RO. This bit is cleared in non FIFO mode. This bit is
connected to BI bit in FIFO mode.
6
Transmit Shift Register Empty (TEMT)— RO. This bit is connected by HW to bit 5
(THRE) of this register.
5
Transmit Holding Register Empty (THRE)— RO. This bit is always set when the
mode (FIFO/Non-FIFO) is changed by the Host. This bit is active only when the THR
operation is enabled by the FW. This bit has acts differently in the different modes:
Non FIFO: This bit is cleared by hardware when the Host writes to the THR registers
and set by hardware when the FW reads the THR register.
FIFO mode: This bit is set by hardware when the THR FIFO is empty, and cleared by
hardware when the THR FIFO is not empty.
This bit is reset on Host system reset or D3->D0 transition.
4
Break Interrupt (BI)— RO. This bit is cleared by hardware when the LSR register is
being read by the Host.
This bit is set by hardware in two cases:
• In FIFO mode the FW sets the BI bit by setting the SBI bit in the KTRIVR register
(See KT AUX registers)
• In non-FIFO mode the FW sets the BI bit by setting the BIA bit in the KTRxBR
register (see KT AUX registers)
3:2 Reserved
1
Overrun Error (OE): This bit is cleared by hardware when the LSR register is being
read by the Host. The FW typically sets this bit, but it is cleared by hardware when
the host reads the LSR.
0
Data Ready (DR)— RO.
Non-FIFO Mode: This bit is set when the FW writes to the RBR register and cleared
by hardware when the RBR register is being Read by the Host.
FIFO Mode: This bit is set by hardware when the RBR FIFO is not empty and cleared
by hardware when the RBR FIFO is empty.
This bit is reset on Host System Reset or D3->D0 transition.