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Schweitzer Engineering Laboratories SEL-421-4 - Firmware

Schweitzer Engineering Laboratories SEL-421-4
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Date Code 20171021 Instruction Manual SEL-421 Relay
List of Tables
Table 11.68 Relay Word Bits: Bay Control Disconnect Timers and Breaker Status ..................................11.72
Table 11.69 Under/Overvoltage Elements ..................................................................................................11.76
Table 11.70 Relay Word Bits: 81 Frequency Elements ..............................................................................11.77
Table 11.71 Full-Cycle Mho and Quad Distance ........................................................................................11.78
Table 11.72 Time and Date Management....................................................................................................11.79
Table 11.73 Remote Axion Status ...............................................................................................................11.79
Table 11.74 Additional Inputs and Outputs.................................................................................................11.79
Table 12.1 Analog Quantities Sorted Alphabetically ..................................................................................12.1
Table 12.2 Analog Quantities Sorted by Function ....................................................................................12.12
Table A.1 Firmware Revision History ........................................................................................................A.2
Table A.2
SELBOOT Revision History ..............................................................................................
.........A.9
Table A.3
ICD File Revision History.................................
........................................................................A.9
Table A.4
Instruction Manual Revision History ..............................................
.........................................A.10
Table B.1 Relay Word Bit Differences .......................................................................................................B.1
Table B.2 Analog Quantity Differences......................................................................................................B.2
Table B.3 Global Settings Differences........................................................................................................B.3
Table B.4 Group Settings Differences ........................................................................................................B.3
Table B.5 Serial Port Settings Differences..................................................................................................B.4
Table B.6 Ethernet Port Settings Differences .............................................................................................B.4
Table B.7 Binary Inputs Point Mapping for MAPSEL = B ........................................................................B.6
Table B.8 Binary Inputs Point Mapping for MAPSEL = E ........................................................................B.7
Table B.9 Binary Outputs Point Mapping...................................................................................................B.7
Table B.10 Counters Point Mapping.............................................................................................................B.9
Table B.11 Analog Inputs Point Mapping.....................................................................................................B.9
Table B.12 Analog Outputs Point Mapping................................................................................................B.13
Table B.13 Binary Outputs Mapping for DNP3 LAN/WAN......................................................................B.14
Table B.14 IEC 61850 Functional Differences ...........................................................................................B.16
Table B.15 Default Dataset Differences..................................................................................................... .B.16
Table B.16 Logical Node Mapping Differences .........................................................................................B.16

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