Schweitzer Engineering Laboratories SEL-421-4 - Figure 2.28 4 U Rear Panel, Main Board, INT8 I;O Interface Board; Figure 2.29 5 U Rear Panel, Main Board, INT3 and INT1 I;O Interface Board

Firmware13

Metering16

Features21

Circuit Breaker Monitor23

Applications27

Sel Boot28

Table 8.21 DNP31

Models and Options31

Figure 1.1 SEL-421 Functional Overview32

Specifications33

Figure 1.3 Single Circuit Breaker Configuration (ESS := 1)38

Figure 1.5 Double Circuit Breaker Configuration (ESS := 3)39

Figure 1.4 Single Circuit Breaker Configuration with Line Breaker Cts (ESS := 2)39

Figure 1.6 Double Circuit Breaker Configuration with Bus Protection (ESS := 4)40

Figure 1.7 Tapped Line (ESS40

Table 1.1 Application Highlights41

Table 1.2 SEL-421 Relay Characteristics43

Station DC Battery System Monitor49

Shared Configuration Attributes51

Figure 2.1 Horizontal Front-Panel Template (A); Vertical Front-Panel Template53

Figure 2.2 Rear 3U Template, Fixed Terminal Block Analog Inputs54

Figure 2.3 Rear 3U Template, Connectorized Analog Inputs55

Table 2.1 Recommended Control Input Pickup Settings56

Table 2.2 Required Settings for Use with AC Control Signals57

Figure 2.4 Standard Control Output Connection58

Figure 2.5 Hybrid Control Output Connection59

Figure 2.6 High-Speed, High-Current Interrupting Control Output Connection, INT5 (INT8)60

Figure 2.7 High-Speed, High-Current Interrupting Control Output Connection, INT460

Figure 2.8 High-Speed, High-Current Interrupting Control Output Typical Terminals, INT5 (INT8)61

Figure 2.9 Precharging Internal Capacitance of High-Speed, High-Current Interrupting Output61

Figure 2.10 INT1 I/O Interface Board63

Figure 2.11 INT2 I/O Interface Board63

Figure 2.12 INT3 I/O Interface Board63

Plug-In Boards63

Figure 2.17 INT8 I/O Interface Board64

Figure 2.16 INT7 I/O Interface Board64

Figure 2.15 INT6 I/O Interface Board64

Figure 2.14 INT5 I/O Interface Board64

Figure 2.13 INT4 I/O Interface Board64

Table 2.3 Control Inputs65

Table 2.4 Control Outputs65

Jumpers65

Table 2.5 Main Board Jumpers66

Figure 2.18 Jumper Location on the Main Board66

Figure 2.19 Major Component Locations on the SEL-421 Main Board68

Table 2.6 Main Board Jumpers-JMP2, JMP3, and JMP469

Figure 2.20 Major Component Locations on the SEL-421 INT1, INT2, INT4, INT5, INT6, INT7, and INT8 I/O Boards71

Figure 2.21 Major Component Locations on the SEL-421 INT3 I/O Board72

Table 2.9 Jumper Positions for Arc Suppression73

Table 2.8 Jumper Positions for Breaker OPEN/CLOSE Indication73

Table 2.7 I/O Board Jumpers73

Table 2.10 Front-Panel LED Option74

Relay Placement74

Figure 2.22 SEL-421 Chassis Dimensions75

Connection75

Figure 2.23 3U Rear Panel, Main Board76

Figure 2.24 3U Rear Panel, Main Board, Connectorized76

Figure 2.25 Ethercat Board for Tidl77

Figure 2.26 4U Rear Panel, Main Board, Without Optional I77

Figure 2.27 4U Rear Panel, Main Board, INT5 I/O Interface Board77

Figure 2.28 4U Rear Panel, Main Board, INT8 I/O Interface Board78

Figure 2.29 5U Rear Panel, Main Board, INT3 and INT1 I/O Interface Board78

Figure 2.30 5U Rear Panel, Main Board, INT4 and INT1 I/O Interface Board79

Figure 2.31 5U Rear Panel, Main Board, INT6 and INT4 I/O Interface Board79

Figure 2.32 5U Rear Panel, Main Board, INT2 and INT7 I/O Interface Board80

Figure 2.33 Rear-Panel Symbols80

Figure 2.34 Screw-Terminal Connector Keying81

Figure 2.35 Rear-Panel Receptacle Keying82

Figure 2.36 Power Connection Area of the Rear Panel83

Table 2.11 Fuse Requirements for the Power Supply84

Figure 2.37 Control Output OUT10886

Figure 2.38 Axion Chassis88

Figure 2.39 SEL-2243 Power Coupler89

Figure 2.40 SEL-2244-2 Digital Input Module90

Figure 2.41 SEL-2244-5 Fast High-Current Digital Output Module91

Figure 2.42 SEL-2245-42 AC Analog Input Module92

Figure 2.43 Topology 193

Figure 2.44 Topology 293

Figure 2.45 Topology 394

Table 2.12 Tidl LED Status95

Figure 2.46 Remote Module Interface95

Figure 2.47 SEL-421 to Computer-D-Subminiature 9-Pin Connector97

Figure 2.48 Example Ethernet Panel with Fiber-Optic Ports98

Figure 2.54 100BASE-FX and 10/100BASE-T Port Configuration on Ports 5C and 5D99

Figure 2.53 Two 10/100BASE-T Port Configuration on Ports 5C and 5D99

Figure 2.52 Two 100BASE-FX Port Configuration on Ports 5C and 5D99

Figure 2.51 100BASE-FX and 10/100BASE-T Port Configuration on Ports 5A and 5B99

Figure 2.50 Two 10/100BASE-T Port Configuration on Ports 5A and 5B99

Figure 2.49 Two 100BASE-FX Port Configuration on Ports 5A and 5B99

AC/DC Connection Diagrams100

Figure 2.55 Typical External AC/DC Connections-Single Circuit Breaker101

Figure 2.56 Typical External AC/DC Connections-Dual Circuit Breaker102

Figure 2.57 SEL-421 Example Wiring Diagram Using the Auxiliary TRIP/CLOSE Pushbuttons103

Low-Level Test Interface105

Table 3.1 UUT Database Entries for SEL-5401 Relay Test System Software-5 a Relay106

Table 3.2 UUT Database Entries for SEL-5401 Relay Test System Software-1 a Relay106

Figure 3.1 Low-Level Test Interface106

Relay Test Connections107

Figure 3.2 Test Connections Using Three Voltage and Three Current Sources108

Figure 3.3 Test Connections Using Two Current Sources for Phase-To-Phase, Phase-To-Ground, and Two-Phase-To-Ground Faults109

Figure 3.4 Test Connections Using Two Current Sources for Three-Phase Faults110

Figure 3.5 Test Connections Using a Single Current Source for a Phase-To-Ground Fault111

Figure 3.6 Test Connections Using a Single Current Source for a Phase-To-Phase Fault112

Checking Relay Operation112

Figure 3.7 Negative-Sequence Instantaneous Overcurrent Element Settings: Quickset114

Figure 3.8 Uploading Group 1 Settings to the SEL-421115

Figure 3.9 ELEMENT SEARCH Screen115

Figure 3.10 RELAY ELEMENTS Screen Containing Element 50Q1116

Figure 3.11 Group 1 Relay Configuration Settings: Quickset118

Figure 3.12 Breaker 1 Breaker Monitor Settings: Quickset119

Figure 3.13 Group 1 Line Configuration Settings: Quickset120

Table 3.3 Negative-Sequence Directional Element Settings AUTO Calculations121

Figure 3.14 Directional Settings: Quickset121

Figure 3.15 Uploading Group 1 and Breaker Monitor Settings to the SEL-421122

Figure 3.16 RELAY ELEMENTS LCD Screen Containing Elements F32Q and R32Q122

Figure 3.17 Finding Phase-To-Phase Test Quantities124

Figure 3.18 Phase-Distance Elements Settings: Quickset125

Figure 3.19 RELAY ELEMENTS LCD Screen Containing Element MBC2126

Technical Support127

Front-Panel LCD Default Displays129

Table 4.1 Metering Screens Enable Settings130

Figure 4.1 Sample ROTATING DISPLAY131

Front-Panel Menus and Screens131

Target Leds137

Table 4.2 Front-Panel Target Leds138

Figure 4.9 Factory-Default Front-Panel Target Areas (16 or 24 Leds)138

Table 4.3 TIME Target LED Trigger Elements-Factory Defaults139

Table 4.4 Operator Control Pushbuttons and Leds-Factory Defaults141

Figure 4.10 Operator Control Pushbuttons and Leds (8 or 12 Pushbuttons)141

Front-Panel Operator Control Pushbuttons141

Figure 4.11 Factory-Default Operator Control Pushbuttons143

One-Line Diagrams143

Figure 4.12 Bay Control Screen Selected for Rotating Display144

Figure 4.13 Configuring PB1_HMI for Direct Bay Control Access145

Figure 4.14 Pole Discrepancy146

Figure 4.15 Bay with Ground Switch (Option 1)147

Figure 4.16 Bay Without Ground Switch (Option 2)147

Figure 4.17 Tie Breaker Bay (Option 3)148

Figure 4.18 Bay with Ground Switch (Option 4)148

Figure 4.19 Bay Without Ground Switch (Option 5)149

Figure 4.20 Transfer Bay (Option 6)149

Figure 4.21 Tie Breaker Bay (Option 7)150

Figure 4.22 Bay with Ground Switch (Option 8)150

Figure 4.23 Bay Without Ground Switch (Option 9)151

Figure 4.24 Bay with Ground Switch (Option 10)151

Figure 4.25 Bay Without Ground Switch (Option 11)152

Figure 4.26 Left Breaker Bay with Ground Switch (Option 12)152

Figure 4.28 Middle Breaker Bay (Option 14)153

Figure 4.27 Right Breaker Bay with Ground Switch (Option 13)153

Figure 4.29 Left Breaker Bay Without Ground Switch (Option 15)154

Figure 4.30 Right Breaker Bay Without Ground Switch (Option 16)154

Figure 4.31 Bay with Ground Switch (Option 17)155

Figure 4.32 Bay Without Ground Switch (Option 18)155

Figure 4.33 Left Breaker Bay with Ground Switch (Option 19)156

Figure 4.34 Left Breaker Bay Without Ground Switch (Option 20)156

Figure 4.35 Right Breaker Bay with Ground Switch (Option 21)157

Figure 4.36 Right Breaker Bay Without Ground Switch (Option 22)157

Figure 4.37 Source Transfer (Option 23)158

Figure 4.38 Throw-Over Bus Type 1 Switch (Option 24)158

Figure 4.39 Throw-Over Bus Type 2 Switch (Option 25)159

Figure 4.40 Screen 1159

Figure 4.41 Screen 2160

Figure 5.1 Current and Voltage Source Connections for the SEL-421 Relay162

Figure 5.2 Main and Alternate Line-Current Source Assignments163

Figure 5.3 Combined Currents for Line-Current Source Assignment163

Figure 5.4 Breaker Current Source Assignments163

Table 5.1 Available Current Source Selection Settings Combinations164

Table 5.2 Available Current Source Selection Settings Combinations When ESS := Y, NUMBK := 1164

Table 5.3 Available Current Source Selection Settings Combinations When ESS := Y, NUMBK := 2165

Table 5.4 Available Voltage Source Selection Setting Combinations166

Figure 5.5 ESS := 1, Single Circuit Breaker Configuration168

Table 5.6 ESS := 1, Current and Voltage Source Selection168

Table 5.5 ESS := N, Current and Voltage Source Selection168

Table 5.7 ESS := 2, Current and Voltage Source Selection169

Figure 5.6 ESS := 2, Single Circuit Breaker Configuration169

Table 5.8 ESS := 3, Current and Voltage Source Selection170

Figure 5.7 ESS := 3, Double Circuit Breaker Configuration170

Table 5.9 ESS := 4, Current and Voltage Source Selection171

Figure 5.8 ESS := 4, Double Circuit Breaker Configuration171

Figure 5.9 Tapped EHV Overhead Transmission Line172

Figure 5.10 ESS := Y, Tapped Line172

Table 5.10 ESS := Y, Tapped Line173

Table 5.11 ESS := Y, Current Polarizing Source173

Figure 5.11 ESS := Y, Single Circuit Breaker with Current Polarizing Source Tapped Power Transformer173

Polarizing Quantity for Distance Element Calculations174

Table 5.12 VMEMC Relay Setting175

Frequency Estimation175

Table 5.13 Frequency Measurement and Frequency Tracking Ranges176

Table 5.14 Frequency Estimation176

Figure 5.12 SEL-421 Alpha Quantity Calculation176

Table 5.15 Voltage and Breaker Pole Correlation177

Table 5.16 Frequency Estimation Outputs177

Undervoltage Supervision Logic177

Figure 5.13 Undervoltage Supervision Logic178

Table 5.17 Table Y12. Summary of the Valpha and 81UVSP Calculations179

Over- and Underfrequency Elements179

Figure 5.14 Frequency Element Logic180

Table 5.18 Time-Error Calculation Inputs and Outputs181

Figure 5.15 Sample TEC Command Response182

Figure 5.16 Sample TEC N Command Response182

Table 5.19 Fault Location Triggering Elements183

Table 5.20 Fault Type184

Table 5.21 Fault Location Settings184

Table 5.22 Fault Location Relay Word Bit184

Open-Phase Detection Logic184

Table 5.23 Open-Phase Detection Relay Word Bits185

Table 5.24 Pole-Open Logic Settings185

Table 5.25 EPO Setting Selections185

Table 5.26 Pole-Open Logic Relay Word Bits185

Figure 5.17 Pole-Open Logic Diagram187

Loss-Of-Potential Logic188

Table 5.27 LOP Logic Setting189

Table 5.28 LOP Logic Relay Word Bits189

Figure 5.18 LOP Logic Process Overview190

Figure 5.19 LOP Logic192

Table 5.29 Fault Type Identification Logic Settings193

Table 5.30 FIDS Relay Word Bits193

Table 5.31 Directional Elements Supervising Ground Elements193

Table 5.32 Ground Directional Element Settings194

Table 5.33 Ground Directional Element Settings AUTO Calculations195

Table 5.34 Ground Directional Element Preferred Settings195

Table 5.35 Ground Directional Element Enables197

Figure 5.20 32Q and 32QG Enable Logic Diagram198

Figure 5.21 32V and 32I Enable Logic Diagram198

Table 5.36 Ground Directional Element Relay Word Bits199

Figure 5.22 Best Choice Ground Directional Element Logic200

Figure 5.23 Negative-Sequence Voltage-Polarized Directional Element Logic201

Figure 5.24 Zero-Sequence Voltage-Polarized Directional Element Logic201

Figure 5.25 Zero-Sequence Current-Polarized Directional Element Logic202

Figure 5.26 Ground Directional Element Output Logic Diagram202

Table 5.39 Phase and Negative-Sequence Directional Elements Relay Word Bits205

Figure 5.27 32P, Phase Directional Element Logic Diagram206

Figure 5.28 32Q, Negative-Sequence Directional Element Logic Diagram206

Directionality206

Table 5.40 Zone Directional Settings207

Table 5.41 CVT Transient Detection Logic Setting207

Table 5.42 CVT Transient Detection Logic Relay Word Bit208

Figure 5.29 CVT Transient Detection Logic208

Series-Compensation Line Logic208

Table 5.43 Series-Compensation Line Logic Relay Settings209

Figure 5.30 Load-Encroachment Logic Diagram209

Table 5.44 Load-Encroachment Logic Relay Settings210

Table 5.45 Load-Encroachment Logic Relay Word Bits210

Figure 5.31 Load-Encroachment Characteristics210

Out-Of-Step Logic (Conventional)210

Figure 5.32 OOS Characteristics211

Table 5.46 OOS Logic Relay Settings212

Table 5.47 OOS Logic Relay Word Bits213

Figure 5.33 OOS Positive-Sequence Measurements214

Figure 5.34 OOS Override Logic214

Figure 5.35 OOS Logic Diagram215

Figure 5.36 Open-Pole OSB Unblock Logic216

Figure 5.37 Zero-Setting OOS Blocking Function216

Out-Of-Step Logic (Zero Settings)216

Figure 5.38 Swing Center Voltage Slope Detection Logic218

Figure 5.39 Starter Zone Characteristic219

Figure 5.40 Swing Signature Detector Logic220

Figure 5.41 Swing Signature Detector Logic221

Figure 5.42 Reset Conditions Logic222

Figure 5.43 Type of Power Swings Detected by the DOSB Function223

Figure 5.44 Dependable Power-Swing Block Detector Logic (EOOS = Y1)224

Figure 5.45 Dependable Power-Swing Block Detector Logic (EOOS225

Figure 5.46 Relay Word Bit DOSB Is the or Combination of DOSBY1 and DOSBY225

Figure 5.47 Logic Diagram of the Three-Phase Fault Detector226

Figure 5.48 Pole-Open OOS Blocking Logic226

Table 5.48 Input/Output Combinations of the Pole-Open OOS Blocking Logic227

Figure 5.49 I0/IA2 Angle Supervision During Pole-Open Situation227

Figure 5.50 Blocking of the MAG Signal by the OSBA Fault Detection227

Figure 5.51 Unblocking of the MAB Signal by the 67QUB Element228

Figure 5.52 Directional Element Signals 67QUBF and 67QUBR228

Figure 5.53 OST Scheme Logic Resistive and Reactive Blinders229

Figure 5.54 Logic that Determines Positive-Sequence Impedance Trajectory (EOOS = Y1)230

Figure 5.55 Out-Of-Step Trip Logic (EOOS = Y1)231

Figure 5.56 Out-Of-Step Blocking for Zone 1 through Zone 5232

Mho Ground-Distance Elements232

Table 5.49 Mho Ground-Distance Elements Relay Word Bits233

Figure 5.57 Zone 1 Mho Ground-Distance Element Logic Diagram234

Figure 5.58 Zone 2 Mho Ground-Distance Element Logic Diagram235

Figure 5.59 Zones 3, 4, and 5 Mho Ground-Distance Element Logic Diagram236

Quadrilateral Ground-Distance Elements236

Table 5.50 Differences between the Adaptive Right Resistance Blinder and the Existing Resistance237

Table 5.51 Quadrilateral Ground-Distance Elements Relay Word Bits237

Figure 5.60 Zone 1 Quadrilateral Ground-Distance Element Logic Diagram238

Figure 5.61 Zone 2 Quadrilateral Distance Element Logic Diagram239

Figure 5.62 Zones 3, 4, and 5 Quadrilateral Ground-Distance Element Logic240

Mho Phase-Distance Elements240

Table 5.52 Mho Phase-Distance Elements Relay Word Bits241

Figure 5.63 Zone 1 Mho Phase-Distance Element Logic Diagram242

Figure 5.64 Zone 2 Mho Phase-Distance Element Logic Diagram243

Figure 5.65 Zones 3, 4, and 5 Mho Phase-Distance Element Logic Diagram244

Table 5.53 High-Speed and Conventional Element Directional Setting Summary245

Quadrilateral Phase-Distance Elements245

Figure 5.66 Quadrilateral Phase-Distance Element Characteristic (TANGP = 0)246

Figure 5.67 Quadrilateral Phase-Distance Element Characteristic (TANGP = -10 Degrees)247

Figure 5.68 Network to Determine Homogeneity247

Figure 5.69 Tilt in Apparent Fault Impedance Resulting from Nonhomogeneity248

Table 5.54 Quadrilateral Phase-Distance Elements Relay Word Bits249

Figure 5.70 Zone 1 AB Loop Conventional Quadrilateral Phase-Distance Element Logic250

Figure 5.71 Zone 2 AB Loop Conventional Quadrilateral Phase-Distance Element Logic250

Figure 5.72 Zone 3, 4, and 5 AB Loop Conventional Quadrilateral Phase-Distance Element Logic251

Zone Time Delay251

Figure 5.73 Zone Timers253

Instantaneous Line Overcurrent Elements253

Table 5.55 Phase Overcurrent Element Settings254

Table 5.56 Negative-Sequence Overcurrent Element Settings254

Table 5.59 Negative-Sequence Instantaneous/Definite-Time Line Overcurrent Relay Word Bits255

Table 5.58 Phase Instantaneous/Definite-Time Line Overcurrent Relay Word Bits255

Table 5.57 Residual Ground Overcurrent Element Settings255

Table 5.60 Residual Ground Instantaneous/Definite-Time Line Overcurrent Relay Word Bits256

Figure 5.74 Phase Instantaneous/Definite-Time Overcurrent Elements257

Figure 5.75 Residual Ground Instantaneous/Directional Overcurrent Elements258

Figure 5.76 Negative-Sequence Instantaneous/Directional Overcurrent Elements259

Inverse-Time Overcurrent Elements259

Table 5.61 Selectable Current Quantities260

Table 5.62 Selectable Inverse-Time Overcurrent Settings260

Table 5.63 Selectable Inverse-Time Overcurrent Relay Word Bits261

Table 5.64 Equations Associated with U.S. Curves261

Table 5.65 Equations Associated with IEC Curves262

Figure 5.77 U.S. Moderately Inverse-U1263

Figure 5.78 U.S. Inverse-U2264

Figure 5.79 U.S. very Inverse-U3265

Figure 5.80 U.S. Extremely Inverse-U4266

Figure 5.81 U.S. Short-Time Inverse-U5267

Figure 5.82 IEC Standard Inverse-C1268

Figure 5.83 IEC very Inverse-C2269

Figure 5.84 IEC Extremely Inverse-C3270

Figure 5.85 IEC Long-Time Inverse-C4271

Figure 5.86 IEC Short-Time Inverse-C5272

Figure 5.87 Selectable Inverse-Time Overcurrent Element Logic Diagram273

Figure 5.88 Undervoltage Elements273

Over- and Undervoltage Elements273

Table 5.66 Available Input Quantities274

Figure 5.89 Overvoltage Elements274

Switch-Onto-Fault Logic277

Table 5.67 SOTF Settings278

Table 5.68 SOTF Relay Word Bits278

Figure 5.90 SOTF Logic Diagram279

Table 5.69 ECOMM Setting280

Figure 5.91 Required Zone Directional Settings280

Communications-Assisted Tripping Logic280

Directional Comparison Blocking Scheme281

Table 5.70 DCB Settings283

Table 5.71 DCB Relay Word Bits283

Permissive Overreaching Transfer Tripping Scheme284

Figure 5.92 DCB Logic Diagram284

Table 5.72 POTT Settings287

Table 5.73 POTT Relay Word Bits288

Figure 5.93 Permissive Trip Receiver Logic Diagram289

Figure 5.94 POTT Logic Diagram290

Figure 5.95 POTT Cross-Country Logic Diagram291

Figure 5.96 POTT Scheme Logic (ECOMM := POTT3) with Echo and Weak Infeed292

Directional Comparison Unblocking Scheme Logic293

Table 5.74 DCUB Settings294

Table 5.75 DCUB Relay Word Bits295

Figure 5.97 Permissive Trip Received Logic Diagram295

Figure 5.98 DCUB Logic Diagram296

Table 5.76 Additional Settings for Single Pole Tripping (SPT)297

Trip Logic297

Table 5.77 Setting TULO Unlatch Trip Options299

Table 5.78 Trip Logic Settings300

Figure 5.99 Trip Logic Diagram302

Table 5.79 Trip Logic Relay Word Bits304

Figure 5.100 Two Circuit Breakers Trip Logic Diagram305

Figure 5.101 Trip a Unlatch Logic306

Figure 5.102 Trip During Open Pole306

Circuit Breaker Failure Protection306

Figure 5.103 Scheme 1 Logic Diagram307

Figure 5.104 Scheme Y1 Circuit Breaker Failure Logic308

Figure 5.105 Scheme 2 Three-Pole Circuit Breaker Failure Protection Logic309

Figure 5.106 Scheme Y2 Three-Pole Circuit Breaker Failure Logic309

Figure 5.107 Scheme 2 Single-Pole Circuit Breaker Failure Protection Logic310

Figure 5.108 Scheme Y2 Single-Pole Circuit Breaker Failure Protection Logic310

Figure 5.109 Scheme 2 Current-Supervised Three-Pole Retrip Logic311

Figure 5.110 Scheme Y2 Current-Supervised Three-Pole Retrip Logic311

Figure 5.111 Scheme 2 Current-Supervised Single-Pole Retrip Logic311

Figure 5.112 Scheme Y2 Current-Supervised Single-Pole Retrip Logic312

Figure 5.113 no Current/Residual Current Circuit Breaker Failure Protection Logic Diagram312

Table 5.80 Circuit Breaker Failure Relay Word Bits315

Figure 5.114 Circuit Breaker Failure Seal-In Logic Diagram316

Figure 5.117 Circuit Breaker Failure Trip Logic Diagram317

Figure 5.116 Flashover Protection Logic Diagram317

Figure 5.115 Failure to Interrupt Load Current Logic Diagram317

Figure 5.118 Partial Breaker-And-A-Half or Partial Ring-Bus Breaker Arrangement318

Synchronism Check318

Figure 5.119 Synchronism-Check Voltages for Two Circuit Breakers319

Figure 5.120 Synchronism-Check Settings320

Table 5.81 Synchronism-Check Relay Word Bits321

Figure 5.121 Synchronism-Check Relay Word Bits321

Figure 5.122 Example Synchronism-Check Voltage Connections to the SEL-421323

Figure 5.123 Synchronism-Check Voltage Reference324

Figure 5.124 Normalized Synchronism-Check Voltage Sources VS1 and VS2325

Figure 5.125 Healthy Voltage Window and Indication326

Figure 5.126 Synchronism-Check Voltage Difference Logic326

Figure 5.127 Synchronism-Check Enable Logic328

Figure 5.128 "No Slip" System Synchronism-Check Element Output Response330

Figure 5.129 "Slip-No Compensation" Synchronism-Check Element Output Response331

Figure 5.130 "Slip-With Compensation" Synchronism-Check Element Output Response333

Figure 5.131 Alternative Synchronism-Check Source 2 Example and Settings335

Figure 6.1 230 Kv Overhead Transmission Line337

Kv Overhead Distribution Line Example337

Table 6.1 System Data-230 Kv Overhead Transmission Line338

Table 6.2 Secondary Impedances338

Figure 6.2 Circuit Breaker Arrangement at Station339

Table 6.3 LOP Enable Options342

Table 6.4 Options for Enabling Pole-Open Logic348

Table 6.5 Setting TULO Unlatch Trip Options350

Table 6.6 Settings for 230 Kv Overhead TX Example351

Kv Parallel Transmission Lines with Mutual Coupling Example354

Table 6.7 System Data-500 Kv Parallel Overhead Transmission Lines355

Figure 6.3 500 Kv Parallel Overhead Transmission Lines355

Table 6.8 Secondary Impedances356

Figure 6.4 Circuit Breaker-And-A-Half Arrangement: Station S, Line 1358

Table 6.9 LOP Enable Options361

Figure 6.5 Quadrilateral Ground-Distance Element Reactive Reach Setting364

Figure 6.6 Definition of Homogeneous Network366

Table 6.10 Tilt Resulting from Nonhomogeneity367

Figure 6.7 Tilt in Apparent Fault Impedance Resulting from Nonhomogeneity367

Figure 6.8 Nonhomogeneous Angle Setting368

Table 6.11 Options for Enabling Pole-Open Logic373

Table 6.12 Trip Unlatch Options378

Figure 6.9 Current Distribution During Cross-Country Fault380

Figure 6.10 Simplified POTT Scheme KEY1/KEY3 Logic381

Table 6.13 Settings for 500 Kv Parallel TX Example383

Kv Tapped Overhead Transmission Line Example389

Table 6.14 System Data-345 Kv Tapped Overhead Transmission Line390

Figure 6.11 345 Kv Tapped Overhead Transmission Line390

Table 6.15 Secondary Impedances391

Figure 6.12 Circuit Breaker Arrangement at Station393

Table 6.16 LOP Enable Options396

Table 6.17 Local Zone 2 Fault Impedance Measurements398

Figure 6.13 Reverse Zone 3 Coordination398

Table 6.18 Apparent Impedance Measurement for Remote Faults399

Figure 6.14 Impedance Diagram399

Figure 6.15 Load-Encroachment Function403

Figure 6.16 345 Kv Tapped Line Negative-Sequence Network409

Figure 6.17 345 Kv Tapped Line Zero-Sequence Network411

Table 6.19 Options for Enabling Pole-Open Logic413

Figure 6.18 DC Schematic for DCB Trip Scheme416

Table 6.20 Setting TULO Unlatch Trip Options417

Table 6.21 Settings for 345 Kv Tapped TX Example419

EHV Parallel 230 Kv Underground Cables Example423

Figure 6.19 230 Kv Parallel Underground Cables423

Table 6.22 System Data-230 Kv Parallel Underground Cables423

Table 6.23 Secondary Impedances424

Figure 6.20 Circuit Breaker Arrangement at Station S, Cable 1426

Table 6.24 LOP Enable Options429

Figure 6.21 Quadrilateral Ground-Distance Element Reactive Reach Setting431

Figure 6.22 Circuit to Determine Network Homogeneity433

Table 6.25 Tilt Resulting from Nonhomogeneity434

Figure 6.23 Apparent Fault Impedance Resulting from Nonhomogeneity434

Figure 6.24 Nonhomogeneous Angle Setting435

Table 6.26 XAG Measurement for Remote AG Fault437

Figure 6.25 External Ground Fault438

Figure 6.26 Negative-Sequence Fault Current Distribution-External Ground Fault441

Figure 6.27 Reverse Unbalanced Fault on Cable Circuit (Shunt Admittance)445

Table 6.29 Options for Enabling Pole-Open Logic446

Table 6.30 Setting TULO Unlatch Trip Options449

Table 6.31 Settings for 230 Kv Parallel Cables Example451

Figure 6.28 500 Kv Power System455

Out-Of-Step Logic Application Examples455

Table 6.32 Positive-Sequence Impedances (Secondary)456

Figure 6.29 OOS Characteristic Settings Parameters457

Figure 6.30 Calculating Setting R1R7459

Figure 6.31 Swing Trajectory to Determine the OSBD Setting461

Figure 6.32 Inner Blinders463

Table 6.33 Automatically Calculated/Hidden Settings465

Table 6.34 Relay Configuration (Group)465

Table 6.35 Out-Of-Step Tripping/Blocking466

Figure 6.33 OST Characteristics467

Table 6.36 Automatically Calculated/Hidden Settings472

Table 6.37 Relay Configuration (Group)472

Table 6.38 Out-Of-Step Tripping/Blocking472

Figure 6.34 230 Kv Example Power System473

Autoreclose Example473

Figure 6.35 Circuit Breaker Arrangement at Station474

Table 6.39 Settings for Autoreclose Example476

Figure 6.36 Potential Sources476

Autoreclose and Synchronism-Check Example477

Figure 6.37 500 Kv Power System477

Figure 6.38 Partial Circuit Breaker-And-A-Half Arrangement at Station S, Line479

Figure 6.39 Potential Sources483

Table 6.40 Settings for Autoreclose and Synchronism Check Example485

Circuit Breaker Failure Application Examples487

Figure 6.40 Scheme 1 All Faults and Scheme 2 Multiphase Fault Timing Diagram490

Figure 6.41 Scheme 2 Single-Phase Fault Timing Diagram491

Figure 6.42 230 Kv Power System for Circuit Breaker Failure Scheme 1491

Table 6.41 Secondary Quantities492

Figure 6.43 Timing Diagram for Setting BFPU1-Scheme 1493

Table 6.42 Settings for Circuit Breaker Failure Example496

Figure 6.44 Circuit Breaker Failure Trip and Circuit Breaker Trip DC Connections496

Figure 6.45 500 Kv Power System for Circuit Breaker Failure Scheme 2498

Table 6.43 Secondary Quantities498

Figure 6.46 Fault Current Distribution through Faulted Line at Station499

Figure 6.47 Timing Diagram for Setting BFPU1-Scheme 2500

Figure 6.48 Timing Sequences for Circuit Breaker Failure Protection Scheme 2501

Table 6.44 Settings for Circuit Breaker Failure Example504

Figure 6.49 Circuit Breaker BK1 DC Connections (Two Trip Coils)504

Figure 6.50 230 Kv Tapped Overhead Transmission Line506

Kv Tapped Transmission Line Application Example506

Figure 6.51 Automatic Restoration Timing Diagram507

Figure 6.52 SEL-421 Inputs509

Table 6.45 Global Settings510

Table 6.46 Breaker Monitor Settings510

Table 6.47 Group Settings511

Figure 6.53 Protection Free-Form SEL OGIC Control Equations514

Table 6.49 Control Inputs515

Table 6.50 Control Outputs (SEL OGIC Control Equations)515

Figure 6.54 Protection Freeform SEL OGIC Control Equations517

Table 7.1 MET Command522

Table 7.2 Instantaneous Metering Quantities-Voltages, Currents, Frequency523

Table 7.3 Instantaneous Metering Quantities-Power524

Figure 7.1 Complex Power (P/Q) Plane524

Table 7.4 Maximum/Minimum Metering Quantities-Voltages, Currents, Frequency, and Powers525

Table 7.5 Demand and Peak Demand Metering Quantities-LINE526

Table 7.6 Energy Metering Quantities-(LINE)526

Table 7.7 Event Report Nonvolatile Storage Capability When ERDIG528

Table 7.8 Event Report Nonvolatile Storage Capability When ERDIG528

Figure 7.2 Fixed Analog Section of the Event Report529

Table 7.9 Event Report Metered Analog Quantities530

Figure 7.3 Digital Section of the Event Report531

Figure 7.4 Sample Digital Portion of the Event Report532

Figure 7.5 Summary Section of the Event Report533

Figure 7.6 Sample Event Summary Report533

Table 7.10 Event Types534

Figure 7.7 Sample Event History535

Table 8.1 Global Settings Changes537

Alias Settings537

Table 8.4 Global Enables538

Table 8.2 Global Settings Categories538

Table 8.3 General Global Settings538

Table 8.5 Station DC1 Monitor (and Station DC2 Monitor)539

Table 8.6 Control Inputs539

Table 8.7 Main Board Control Inputs539

Table 8.8 Interface Board #1 Control Inputs540

Table 8.9 Interface Board #2 Control Inputs540

Table 8.10 Settings Group Selection541

Table 8.11 Frequency Estimation541

Table 8.12 Time-Error Calculation541

Table 8.13 Current and Voltage Source Selection541

Table 8.15 Phasors Included in the Data542

Table 8.14 Synchronized Phasor Configuration Settings542

Table 8.16 Synchronized Phasor Configuration Settings Part 2543

Table 8.17 Synchronized Phasor Recorder Settings543

Table 8.18 Synchronized Phasor Real Time Control Settings544

Table 8.19 Time and Date Management544

Table 8.20 Data Reset Control544

Table 8.22 Breaker Monitor Settings Categories545

Table 8.23 Enables545

Table 8.24 Breaker 1 Inputs545

Breaker Monitor Settings545

Table 8.27 Breaker 1 Contact Wear (and Breaker 2 Contact Wear)546

Table 8.26 Breaker 1 Monitor (and Breaker 2 Monitor)546

Table 8.25 Breaker 2 Inputs546

Table 8.28 Breaker 1 Electrical Operating Time (and Breaker 2 Electrical Operating Time)547

Table 8.29 Breaker 1 Mechanical Operating Time (and Breaker 2 Mechanical Operating Time)547

Table 8.30 Breaker 1 Pole Scatter and Pole Discrepancy547

Table 8.31 Breaker 1 Inactivity Time Elapsed (and Breaker 2 Inactivity Time Elapsed)547

Table 8.32 Breaker 1 Motor Running Time (and Breaker 2 Motor Running Time)547

Table 8.33 Breaker 1 Current Interrupted (and Breaker 2 Current Interrupted)547

Table 8.34 Group Settings Categories548

Group Settings548

Table 8.35 Line Configuration549

Table 8.36 Relay Configuration549

Table 8.38 Quadrilateral Phase-Distance Element Reach551

Table 8.37 Mho Phase-Distance Element Reach551

Table 8.39 Phase-Distance Element Time Delay552

Table 8.40 Mho Ground-Distance Element Reach552

Table 8.41 Quad Ground-Distance Element Reach553

Table 8.42 Zero-Sequence Compensation Factor554

Table 8.43 Ground-Distance Element Time Delay554

Table 8.44 Series Compensation554

Table 8.45 Distance Element Common Time Delay554

Table 8.46 Switch-Onto-Fault Scheme555

Table 8.47 Out-Of-Step Tripping/Blocking555

Table 8.48 Load Encroachment556

Table 8.51 Phase Instantaneous Definite-Time Overcurrent Torque Control557

Table 8.50 Phase Definite-Time Overcurrent Time Delay557

Table 8.49 Phase Instantaneous Overcurrent Pickup557

Table 8.52 Residual Ground Instantaneous Overcurrent Pickup558

Table 8.53 Residual Ground Definite-Time Overcurrent Time Delay558

Table 8.54 Residual Ground Instantaneous Definite-Time Overcurrent Torque Control558

Table 8.55 Negative-Sequence Instantaneous Overcurrent Pickup559

Table 8.56 Negative-Sequence Definite-Time Overcurrent Time Delay559

Table 8.57 Negative-Sequence Instantaneous Definite-Time Overcurrent Torque Control559

Table 8.58 Selectable Operating Quantity Inverse Time Overcurrent Element 1559

Table 8.61 81 Elements561

Table 8.62 under Voltage (27) Element561

Table 8.63 over Voltage (59) Element561

Table 8.66 Pole-Open Detection562

Table 8.65 Directional Control Element562

Table 8.64 Zone/Level Direction562

Table 8.67 POTT Trip Scheme563

Table 8.68 DCUB Trip Scheme563

Table 8.69 DCB Trip Scheme564

Table 8.70 Breaker 1 Failure Logic (and Breaker 2 Failure Logic)564

Table 8.71 Synchronism-Check Element Reference565

Table 8.72 Breaker 1 Synchronism Check565

Table 8.73 Breaker 2 Synchronism Check565

Table 8.74 Recloser and Manual Closing566

Table 8.75 Single-Pole Reclose Settings567

Table 8.76 Three-Pole Reclose Settings567

Table 8.78 Demand Metering568

Table 8.77 Voltage Elements568

Table 8.80 Trip Logic569

Notes Settings570

Table 8.82 Main Board Default Values571

Table 8.83 Front-Panel Settings Defaults571

Output Settings571

Report Settings574

Table 8.85 Bay Settings575

DNP3 Settings—Custom Maps575

Table 9.1 SEL-421 List of Commands578

Description of Commands578

Table 9.2 MET Command580

Table 9.5 MET SYN Command581

Table 9.4 MET RMS Command581

Table 9.3 MET E Command581

Table 9.6 SET Command Overview582

Table 9.7 SHO Command Overview583

Table 10.1 SEL-421 Database Regions585

Communications Database585

Table 10.2 SEL-421 Database Structure-LOCAL Region586

Table 10.3 SEL-421 Database Structure-METER Region586

Table 10.4 SEL-421 Database Structure-DEMAND Region588

Table 10.5 SEL-421 Database Structure-TARGET Region589

Table 10.6 SEL-421 Database Structure-HISTORY Region589

Table 10.8 SEL-421 Database Structure-STATUS Region590

Table 10.7 SEL-421 Database Structure-BREAKER Region590

Table 10.9 SEL-421 Database Structure-ANALOGS Region591

Figure 10.1 MAP 1:METER Command Example592

DNP3 Communication592

Table 10.10 SEL-421 DNP3 Reference Data Map593

Table 10.11 SEL-421 Object 12 Control Operations598

Table 10.12 Object 30, 32, FTYPE Upper Byte-Event Cause600

Table 10.13 Object 30, 32, FTYPE Lower Byte-Affected Phase600

Table 10.14 SEL-421 DNP3 Default Data Map600

Table 10.15 Logical Device: PRO (Protection)606

IEC 61850 Communication606

Table 10.16 Logical Device: MET (Metering)611

Synchrophasors614

Table 10.17 Voltage Synchrophasor Names614

Table 10.18 Current Synchrophasor Names614

Table 10.19 Synchrophasor Order in Data Stream (Voltages and Currents)615

Table 11.1 Alphabetic List of Relay Word Bits617

Alphabetical List617

Table 11.2 Relay Word Bits: Enable and Tripping Bits650

Table 11.3 Relay Word Bits: Distance Elements650

Row Lists650

Table 11.4 Relay Word Bits: Series-Compensated Line Logic653

Table 11.5 Relay Word Bits: Out-Of-Step Elements654

Table 11.6 Relay Word Bits: Directional Elements655

Table 11.8 Relay Word Bits: Synchronism-Check Elements656

Table 11.7 Relay Word Bits: Overcurrent Elements656

Table 11.9 Relay Word Bits: Reclosing Elements657

Table 11.10 Relay Word Bits: Miscellaneous Elements659

Table 11.11 Relay Word Bits: Trip Logic Elements659

Table 11.12 Relay Word Bits: Pilot Tripping Elements661

Table 11.13 Relay Word Bits: Future Breaker Open-Phase Detector662

Table 11.14 Relay Word Bits: Breaker 1 Failure662

Table 11.15 Relay Word Bits: Breaker 2 Failure663

Table 11.16 Relay Word Bits: 52 Status and Open-Phase Detector664

Table 11.17 Relay Word Bits: Breaker Monitoring666

Table 11.18 Relay Word Bits: RTD Status Bits666

Table 11.22 Relay Word Bits: Local Bits667

Table 11.20 Relay Word Bits: Metering Elements667

Table 11.21 Relay Word Bits: Open and Close667

Table 11.19 Relay Word Bits: Battery Monitor667

Table 11.23 Relay Word Bits: Remote Bits668

Table 11.24 Relay Word Bits: Settings Group Bits668

Table 11.25 Relay Word Bits: Future Breaker Failure Bits668

Table 11.26 Relay Word Bits: Input Elements668

Table 11.34 Relay Word Bits: Automation Sequencing Timers670

Table 11.37 Relay Word Bits: Alarms671

Table 11.38 Relay Word Bits: Time and Date Management and Frequency Estimation671

Table 11.39 Relay Word Bits: Pushbuttons and Outputs672

Table 11.43 Relay Word Bits: Target Logic Bits673

Table 11.42 Relay Word Bits: Data Reset Bits673

Table 11.41 Relay Word Bits: Pushbutton LED Bits673

Table 11.44 Relay Word Bits: M674

Table 11.45 Relay Word Bits: Test Bits674

Table 11.46 Relay Word Bits: Virtual Bits674

Table 11.47 Relay Word Bits: Ethernet Switch675

Table 11.48 Relay Word Bits: Signal Profiling676

Table 11.49 Relay Word Bits: Fast SER Enable Bits676

Table 11.50 Relay Word Bits: Source Selection Elements676

Table 11.51 Relay Word Bits: Full-Cycle Mho and Quad Ground-Distance677

Table 11.52 Relay Word Bits: Full-Cycle Mho and Phase Quad Phase-Distance677

Table 11.53 Relay Word Bits: High-Speed Mho and Quad Ground-Distance678

Table 11.54 Relay Word Bits: High-Speed Mho and Quad Phase-Distance679

Table 11.55 Relay Word Bits: DNP Event Lock680

Table 11.57 Relay Word Bits: IRIG-B Control681

Table 11.58 Relay Word Bit: Time-Error Calculation681

Table 11.59 Relay Word Bits: Synchrophasor Configuration Error682

Table 11.60 Relay Word Bits: Pushbuttons, Pushbutton Leds, and Target Leds for New HMI682

Table 11.61 Relay Word Bits: Local Bit Supervision683

Table 11.62 Relay Word Bits: Local Bit Status683

Table 11.63 Relay Word Bits: RTC Remote Digital Status683

Table 11.64 Relay Word Bits: Fast Operate Transmit Bits683

Table 11.65 Relay Word Bits: Bay Control Disconnect Status684

Table 11.67 Relay Word Bits: Bay Control Disconnect Control686

Table 11.66 Relay Word Bits: Bay Control Disconnect Bus-Zone Compliant686

Table 11.68 Relay Word Bits: Bay Control Disconnect Timers and Breaker Status688

Table 11.69 Under/Overvoltage Elements692

Table 11.70 Relay Word Bits: 81 Frequency Elements693

Table 11.71 Full-Cycle Mho and Quad Distance694

Table 11.72 Time and Date Management695

Table 11.73 Remote Axion Status695

Table 11.74 Additional Inputs and Outputs695

Table 12.1 Analog Quantities Sorted Alphabetically697

Table 12.2 Analog Quantities Sorted by Function708

ICD File721

Table A.1 Firmware Revision History722

Table A.2 SEL BOOT Revision History729

Table A.3 ICD File Revision History729

Table A.4 Instruction Manual Revision History730

Table B.1 Relay Word Bit Differences733

Table B.2 Analog Quantity Differences734

Analog Quantity Changes734

Table B.3 Global Settings Differences735

Table B.4 Group Settings Differences735

Global Settings Changes735

Table B.5 Serial Port Settings Differences736

Table B.6 Ethernet Port Settings Differences736

Front-Panel Settings Changes736

Table B.7 Binary Inputs Point Mapping for MAPSEL = B738

DNP3 Mapping Changes738

Table B.8 Binary Inputs Point Mapping for MAPSEL = E739

Table B.9 Binary Outputs Point Mapping739

Table B.10 Counters Point Mapping741

Table B.11 Analog Inputs Point Mapping741

Table B.12 Analog Outputs Point Mapping745

Table B.13 Binary Outputs Mapping for DNP3 LAN/WAN746

Table B.14 IEC 61850 Functional Differences748

Table B.15 Default Dataset Differences748

Table B.16 Logical Node Mapping Differences748

IEC 61850 Object Changes748

Schweitzer Engineering Laboratories SEL-421-4 - Figure 2.28 4 U Rear Panel, Main Board, INT8 I;O Interface Board; Figure 2.29 5 U Rear Panel, Main Board, INT3 and INT1 I;O Interface Board

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