6.133
Date Code 20171021 Instruction Manual SEL-421 Relay
Protection Applications Examples
Out-of-Step Logic Application Examples
Reactance Lines
Set the reactance lines equal to the maximum values to help the relay detect
power swings far from the relay location.
Set the Zone 7 top reactance line equal to the maximum setting.
X1T7 := 96. Zone 7 Reactance—Top (0.05–140 secondary)
Set the Zone 6 top reactance line to the maximum setting minus one ohm.
Equation 6.82
X1T6 := 95. Zone 6 Reactance—Top (0.05–140 secondary)
Out-of-Step Tripping and Blocking
The OOS logic uses two zones of concentric polygons, outer Zone 7 and inner
Zone 6 (see Figure 6.33). The relay uses Zone 6 and Zone 7 for OOS logic timing
to differentiate OOS blocking conditions, OOS tripping conditions, and faults.
The relay measures a traveling positive-sequence impedance locus (Z
1
) in Zone 6
and Zone 7 when a power swing or fault occurs. When the impedance locus ini-
tially moves inside Zone 7, the relay starts two OOS logic timers. One OOS timer
detects OOS blocking conditions (OSBD), while the other timer detects OOS
tripping conditions (OSTD).
NOTE: You must set OSTD shorter
than OSBD by at least a half cycle.
The OOS logic declares a blocking condition if OSBD expires before the posi-
tive-sequence impedance locus enters Zone 6. The logic declares a tripping con-
dition if OSTD expires and the positive-sequence impedance locus enters Zone 6
prior to OSBD timing out.
Trip-On-Way-In/Trip-On-Way-Out
You can select one of two methods to trip during an unstable swing. You can
enable the relay to trip if OSTD expires and the positive-sequence impedance
enters Zone 6; this method is Trip-On-the-Way-In (TOWI in Figure 6.33). The
relay asserts Relay Word bits OSTI and OST for a Trip-On-the-Way-In condition.
You can also enable the relay to trip if OSTD expires and the positive-sequence
impedance enters and exits Zone 6; this second method is Trip-On-the-Way-Out
(TOWO in Figure 6.33). The relay asserts Relay Word bits OSTO and OST for a
Trip-On-the-Way-Out condition. Relay Word bit OST is the OR combination of
OSTI and OSTO (see Out-of-Step Logic (Conventional) on page 5.50).
Trip-On-the-Way-Out (TOWO) is selected for this application example (see
Enable OOS Logic on page 6.131).
Out-of-Step Tripping Time Delay
Use Equation 6.83, Equation 6.84, and Equation 6.85 to calculate the OSTD set-
ting. These equations are derived from the impedance trajectory shown in
Figure 6.33. Line section AB is the transfer impedance, Z
T
. The horizontal
dashed line represents the trajectory of the power swing perpendicular to line sec-
tion AB. The trajectory passes through the midpoint of line section AB.
X1T6 X1T7 1 –=
96 1 –=
95 =
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