GD32VF103 User Manual
507
a device sends a data packet and the packet length exceeds the endpoint’s
maximum packet length.
The USB error flag is set when the following conditions occurs during receiving a
packet:
A received packet has a wrong CRC field
A stuff error detected on USB bus
Timeout when waiting for a response packet
Must be kept at reset value
An ACK response is received or transmitted
A NAK response is received.
A STALL response is received.
Must be kept at reset value
This channel is disabled by a request, and it will not response to other requests
during the request processing.
All the transactions of this channel finish successfully, and no error occurs. For IN
channel, this flag will be triggered after PCNT bits in USBFS_HCHxLEN register
reach zero. For OUT channel, this flag will be triggered when software reads and
pops a TF status entry from the RxFIFO.
Host channel-x interrupt enable register (USBFS_HCHxINTEN) (x = 0..7, where
x = channel number)
Address offset: 0x050C + (channel_number × 0x20)
Reset value: 0x0000 0000
This register contains the interrupt enable bits for the flags in USBFS_HCHxINTF register. If
a bit in this register is set by software, the corresponding bit in USBFS_HCHxINTF register is
able to trigger a channel interrupt. The bits in this register are set and cleared by software.
This register has to be accessed by word (32-bit)
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