GigaDevice Semiconductor GD32VF103 - Page 506

GD32VF103 User Manual
506
15
EPDIR
Endpoint direction
The transfer direction of the endpoint that this channel wants to communicate with.
0: OUT
1: IN
14:11
EPNUM[3:0]
Endpoint number
The number of the endpoint that this channel wants to communicate with.
10:0
MPL[10:0]
Maximum packet length
The target endpoint’s maximum packet length.
Host channel-x interrupt flag register (USBFS_HCHxINTF) (x = 0..7 where x =
channel number)
Address offset: 0x0508 + (channel_number × 0x20)
Reset value: 0x0000 0000
This register contains the status and events of a channel, when software get a channel
interrupt, it should read this register for the respective channel to know the source of the
interrupt. The flag bits in this register are all set by hardware and cleared by writing 1.
This register has to be accessed by word (32-bit)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DTER
REQOVR
BBER
USBER
Reserved.
ACK
NAK
STALL
Reserved.
CH
TF
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits
Fields
Descriptions
31:11
Reserved
Must be kept at reset value
10
DTER
Data toggle error
The IN transaction gets a data packet but the PID of this packet doesn’t match DPID
[1:0] bits in USBFS_HCHxLEN register.
9
REQOVR
Request queue overrun
The periodic request queue is full when software starts new transfers.
8
BBER
Babble error
A babble condition occurs on USB bus. A typical reason for babble condition is that