Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 21

Datasheet 21
17.1.2.16CORBLBASE—CORB Lower Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 717
17.1.2.17CORBUBASE—CORB Upper Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 717
17.1.2.18CORBWP—CORB Write Pointer Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 718
17.1.2.19CORBRP—CORB Read Pointer Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 718
17.1.2.20CORBCTL—CORB Control Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 719
17.1.2.21CORBST—CORB Status Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 719
17.1.2.22CORBSIZE—CORB Size Register
Intel
®
High Definition Audio Controller—D27:F0) ........................ 719
17.1.2.23RIRBLBASE—RIRB Lower Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 720
17.1.2.24RIRBUBASE—RIRB Upper Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 720
17.1.2.25RIRBWP—RIRB Write Pointer Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 720
17.1.2.26RINTCNT—Response Interrupt Count Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 721
17.1.2.27RIRBCTL—RIRB Control Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 721
17.1.2.28RIRBSTS—RIRB Status Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 722
17.1.2.29RIRBSIZE—RIRB Size Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 722
17.1.2.30IC—Immediate Command Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 722
17.1.2.31IR—Immediate Response Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 723
17.1.2.32IRS—Immediate Command Status Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 723
17.1.2.33DPLBASE—DMA Position Lower Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 724
17.1.2.34DPUBASE—DMA Position Upper Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 724
17.1.2.35SDCTL—Stream Descriptor Control Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 725
17.1.2.36SDSTS—Stream Descriptor Status Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 727
17.1.2.37SDLPIB—Stream Descriptor Link Position in Buffer
Register (Intel
®
High Definition Audio Controller—D27:F0)........... 728
17.1.2.38SDCBL—Stream Descriptor Cyclic Buffer Length Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 728
17.1.2.39SDLVI—Stream Descriptor Last Valid Index Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 729
17.1.2.40SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 729
17.1.2.41SDFIFOS—Stream Descriptor FIFO Size Register – Input Streams
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 730
17.1.2.42SDFIFOS—Stream Descriptor FIFO Size Register – Output Streams
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 730
17.1.2.43SDFMT—Stream Descriptor Format Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 731
17.1.2.44SDBDPL—Stream Descriptor Buffer Descriptor List
Pointer Lower Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 732
17.1.2.45SDBDPU—Stream Descriptor Buffer Descriptor List
Pointer Upper Base Address Register
(Intel
®
High Definition Audio Controller—D27:F0) ....................... 732
17.2 Integrated Digital Display Audio Registers and Verb IDs ....................................... 733
17.2.1 Configuration Default Register................................................................ 733
18 SMBus Controller Registers (D31:F3) .................................................................... 739
18.1 PCI Configuration Registers (SMBus—D31:F3)..................................................... 739