Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 22

22 Datasheet
18.1.1 VID—Vendor Identification Register (SMBus—D31:F3)...............................739
18.1.2 DID—Device Identification Register (SMBus—D31:F3) ...............................740
18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) ..................................740
18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) ........................................741
18.1.5 RID—Revision Identification Register (SMBus—D31:F3) .............................741
18.1.6 PI—Programming Interface Register (SMBus—D31:F3) ..............................742
18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)......................................742
18.1.8 BCC—Base Class Code Register (SMBus—D31:F3).....................................742
18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0 (SMBus—D31:F3)......742
18.1.10SMBMBAR1—D31_F3_SMBus Memory Base Address 1 (SMBus—D31:F3)......743
18.1.11SMB_BASE—SMBus Base Address Register
(SMBus—D31:F3) .................................................................................743
18.1.12SVID—Subsystem Vendor Identification Register
(SMBus—D31:F2/F4).............................................................................743
18.1.13SID—Subsystem Identification Register
(SMBus—D31:F2/F4).............................................................................744
18.1.14INT_LN—Interrupt Line Register (SMBus—D31:F3)....................................744
18.1.15INT_PN—Interrupt Pin Register (SMBus—D31:F3).....................................744
18.1.16HOSTC—Host Configuration Register (SMBus—D31:F3)..............................745
18.2 SMBus I/O and Memory Mapped I/O Registers.....................................................746
18.2.1 HST_STS—Host Status Register (SMBus—D31:F3) ....................................747
18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)...................................748
18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) ..............................750
18.2.4 XMIT_SLVA—Transmit Slave Address Register
(SMBus—D31:F3) .................................................................................750
18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) .....................................750
18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) .....................................750
18.2.7 Host_BLOCK_DB—Host Block Data Byte Register
(SMBus—D31:F3) .................................................................................751
18.2.8 PEC—Packet Error Check (PEC) Register
(SMBus—D31:F3) .................................................................................751
18.2.9 RCV_SLVA—Receive Slave Address Register
(SMBus—D31:F3) .................................................................................752
18.2.10SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)........................752
18.2.11AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ..............................752
18.2.12AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) .............................753
18.2.13SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBus—D31:F3) .................................................................................753
18.2.14SMBus_PIN_CTL—SMBus Pin Control Register
(SMBus—D31:F3) .................................................................................754
18.2.15SLV_STS—Slave Status Register (SMBus—D31:F3) ...................................754
18.2.16SLV_CMD—Slave Command Register (SMBus—D31:F3) .............................755
18.2.17NOTIFY_DADDR—Notify Device Address Register
(SMBus—D31:F3) .................................................................................755
18.2.18NOTIFY_DLOW—Notify Data Low Byte Register
(SMBus—D31:F3) .................................................................................756
18.2.19NOTIFY_DHIGH—Notify Data High Byte Register
(SMBus—D31:F3) .................................................................................756
19 PCI Express* Configuration Registers....................................................................757
19.1 PCI Express* Configuration Registers
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................................757
19.1.1 VID—Vendor Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................759
19.1.2 DID—Device Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................759
19.1.3 PCICMD—PCI Command Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................760
19.1.4 PCISTS—PCI Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................761
19.1.5 RID—Revision Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................762
19.1.6 PI—Programming Interface Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................762
19.1.7 SCC—Sub Class Code Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7)...............................762