Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 35

Datasheet 35
8-32 SPI Timings (20 MHz)......................................................................................... 329
8-33 SPI Timings (33 MHz)......................................................................................... 329
8-34 SPI Timings (50 MHz)......................................................................................... 330
8-35 Controller Link Receive Timings ........................................................................... 330
8-36 Power Sequencing and Reset Signal Timings.......................................................... 331
9-1 PCI Devices and Functions .................................................................................. 350
9-2 Fixed I/O Ranges Decoded by Intel
®
PCH.............................................................. 352
9-3 Variable I/O Decode Ranges................................................................................ 354
9-4 Memory Decode Ranges from Processor Perspective............................................... 355
10-1 Chipset Configuration Register Memory Map (Memory Space) .................................. 359
11-1 PCI Bridge Register Address Map (PCI-PCI—D30:F0) .............................................. 415
12-1 Gigabit LAN Configuration Registers Address Map
(Gigabit LAN —D25:F0) ...................................................................................... 433
13-1 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) ..................................... 447
13-2 DMA Registers................................................................................................... 474
13-3 PIC Registers .................................................................................................... 485
13-4 APIC Direct Registers ......................................................................................... 493
13-5 APIC Indirect Registers....................................................................................... 493
13-6 RTC I/O Registers.............................................................................................. 498
13-7 RTC (Standard) RAM Bank .................................................................................. 499
13-8 Processor Interface PCI Register Address Map ....................................................... 503
13-9 Power Management PCI Register Address Map (PM—D31:F0)................................... 506
13-10 APM Register Map.............................................................................................. 515
13-11 ACPI and Legacy I/O Register Map....................................................................... 516
13-12 TCO I/O Register Address Map............................................................................. 534
13-13 Registers to Control GPIO Address Map................................................................. 541
14-1 SATA Controller PCI Register Address Map (SATA–D31:F2)...................................... 551
14-2 Bus Master IDE I/O Register Address Map............................................................. 579
14-3 AHCI Register Address Map................................................................................. 588
14-4 Generic Host Controller Register Address Map........................................................ 589
14-5 Port [5:0] DMA Register Address Map................................................................... 599
15-1 SATA Controller PCI Register Address Map (SATA–D31:F5)...................................... 617
15-2 Bus Master IDE I/O Register Address Map............................................................. 633
16-1 USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) .......................... 641
16-2 Enhanced Host Controller Capability Registers ....................................................... 661
16-3 Enhanced Host Controller Operational Register Address Map.................................... 664
16-4 Debug Port Register Address Map ........................................................................ 678
17-1 Intel
®
High Definition Audio PCI Register Address Map
(Intel
®
High Definition Audio D27:F0) .................................................................. 683
17-2 Intel
®
High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel
®
High Definition Audio D27:F0)................................................ 706
17-3 Configuration Default ......................................................................................... 733
17-4 Configuration Data Structure............................................................................... 733
17-5 Port Connectivity ............................................................................................... 735
17-6 Location ........................................................................................................... 735
17-7 Default Device................................................................................................... 736
17-8 Connection Type................................................................................................ 736
17-9 Color................................................................................................................ 737
17-10 Misc................................................................................................................. 737
18-1 SMBus Controller PCI Register Address Map (SMBus—D31:F3)................................. 739
18-2 SMBus I/O and Memory Mapped I/O Register Address Map...................................... 746
19-1 PCI Express* Configuration Registers Address Map
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ..................................................... 757
20-1 Memory-Mapped Registers.................................................................................. 799
21-1 Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers)....................................................... 809
21-2 Gigabit LAN SPI Flash Program Register Address Map
(GbE LAN Memory Mapped Configuration Registers) ............................................... 832
22-1 Thermal Sensor Register Address Map.................................................................. 845
22-2 Thermal Memory Mapped Configuration Register Address Map ................................. 854
23-1 Intel
®
MEI Configuration Registers Address Map
(MEI — D22:F0) ................................................................................................ 867
23-1 MEI1 Configuration Registers Address Map
(MEI —D22:F1) ................................................................................................. 879
23-2 MEI MMIO Register Address Map (VE — D23:F0).................................................... 888
23-3 MEI MMIO Register Address Map (VE — D23:F0).................................................... 891
23-4 IDE Function for remote boot and Installations PT IDER Register Address Map ........... 894