Chipset Configuration Registers
362 Datasheet
10.1.1 CIR0—Chipset Initialization Register 0
Offset Address: 0050–0053h Attribute: R/WL
Default Value: 00000000h Size: 32-bit
3A80–3A83h CIR27 Chipset Initialization Register 27 00000000h R/W
3A84–3A87h CIR28 Chipset Initialization Register 28 00000000h R/W
3A88–3A8Bh CIR29 Chipset Initialization Register 29 00000000h R/W
Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 4 of 4)
Offset Mnemonic Register Name Default Type
Bit Description
31
TC Lock-Down (TCLOCKDN)— R/WL. When set to 1, certain DMI configuration
registers are locked down by this and cannot be written. Once set to 1, this bit can
only be cleared by a PLTRST#.
30:0 CIR0 Field 0— R/WL. BIOS must set this field. Bits locked by TCLOCKDN.
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