Datasheet 393
Chipset Configuration Registers
10.1.47 PRSTS—Power and Reset Status
Offset Address: 3310–3313h Attribute: RO, R/WC
Default Value: 03000000h Size: 32-bit
10.1.48 CIR7—Chipset Initialization Register 7
Offset Address: 3314–3317h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:16 Reserved
15
Power Management Watchdog Timer — R/WC. This bit is set when the Power
Management watchdog timer causes a global reset.
14:8 Reserved
7
VE Watchdog Timer Status — R/WC. This bit is set when the VE watchdog timer
causes a global reset.
6
Intel
®
Management Engine Watchdog Timer Status — R/WC. This bit is set
when the Intel Management Engine watchdog timer causes a global reset.
5
Wake On LAN Override Wake Status (WOL_OVR_WK_STS) — R/WC. This bit
gets set when all of the following conditions are met:
• Integrated LAN Signals a Power Management Event
• The system is not in S0
• The “WOL Enable Override” bit is set in configuration space.
BIOS can read this status bit to determine this wake source.
Software clears this bit by writing a 1 to it.
4 Reserved
3
Intel ME Host Power Down (ME_HOST_PWRDN) — R/WC. This bit is set when
the Intel Management Engine generates a host reset with power down.
2
Intel ME Host Reset Warm Status (ME_HRST_WARM_STS) — R/WC. This bit is
set when the Intel Management Engine generates a Host reset without power cycling.
Software clears this bit by writing a 1 to this bit position.
1
Intel ME Host Reset Cold Status (ME_HRST_COLD_STS) — R/WC. This bit is set
when the Intel Management Engine generates a Host reset with power cycling.
Software clears this bit by writing a 1 to this bit position.
0
Intel ME WAKE STATUS (ME_WAKE_STS) — R/WC. This bit is set when the Intel
Management Engine generates a Non-Maskable wake event, and is not affected by
any other enable bit. When this bit is set, the Host Power Management logic wakes to
S0.
Bit Description
31:5 Reserved
3:0 CIR7 Field 1— R/W. BIOS must program this field to 1111b.
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