Chipset Configuration Registers
406 Datasheet
10.1.75 CG—Clock Gating
Offset Address: 341C–341Fh Attribute: R/W
Default Value: 00000000h Size: 32-bit
4
Intel
®
High Definition Audio Disable (HDAD) — R/W. Default is 0.
0 = The Intel
®
High Definition Audio controller is enabled.
1 = The Intel
®
High Definition Audio controller is disabled and its PCI configuration
space is not accessible.
3
SMBus Disable (SD) — R/W. Default is 0.
0 = The SMBus controller is enabled.
1 = The SMBus controller is disabled. Setting this bit only disables the PCI
configuration space.
2
Serial ATA Disable 1 (SAD1) — R/W. Default is 0.
0 = The SATA controller #1 (D31:F2) is enabled.
1 = The SATA controller #1 (D31:F2) is disabled.
1
PCI Bridge Disable — R/W. Default is 0.
0 = The PCI-to-PCI bridge (D30:F0) is enabled.
1 = The PCI-to-PCI bridge (D30:F0) is disabled.
0 BIOS must set this bit to 1b.
Bit Description
Bit Description
31
Legacy (LPC) Dynamic Clock Gate Enable — R/W.
0 = Legacy Dynamic Clock Gating is Disabled
1 = Legacy Dynamic Clock Gating is Enabled
30:28 Reserved
27
SATA Port 3 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 3 Dynamic Clock Gating is Disabled
1 = SATA Port 3 Dynamic Clock Gating is Enabled
26
SATA Port 2 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 2 Dynamic Clock Gating is Disabled
1 = SATA Port 2 Dynamic Clock Gating is Enabled
25
SATA Port 1 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 1 Dynamic Clock Gating is Disabled
1 = SATA Port 1 Dynamic Clock Gating is Enabled
24
SATA Port 0 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 0 Dynamic Clock Gating is Disabled
1 = SATA Port 0 Dynamic Clock Gating is Enabled
23
LAN Static Clock Gating Enable (LANSCGE) — R/W.
0 = LAN Static Clock Gating is Disabled
1 = LAN Static Clock Gating is Enabled when the LAN Disable bit is set in the Backed
Up Control RTC register.
22
High Definition Audio Dynamic Clock Gate Enable — R/W.
0 = High Definition Audio Dynamic Clock Gating is Disabled
1 = High Definition Audio Dynamic Clock Gating is Enabled
To Next Page
Loading...