Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 407

Datasheet 407
Chipset Configuration Registers
10.1.76 FDSW—Function Disable SUS Well
Offset Address: 3420h Attribute: R/W
Default Value: 00h Size: 8-bit
21
High Definition Audio Static Clock Gate Enable — R/W.
0 = High Definition Audio Static Clock Gating is Disabled
1 = High Definition Audio Static Clock Gating is Enabled
20
USB EHCI Static Clock Gate Enable — R/W.
0 = USB EHCI Static Clock Gating is Disabled
1 = USB EHCI Static Clock Gating is Enabled
19
USB EHCI Dynamic Clock Gate Enable — R/W.
0 = USB EHCI Dynamic Clock Gating is Disabled
1 = USB EHCI Dynamic Clock Gating is Enabled
18
SATA Port 5 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 5 Dynamic Clock Gating is Disabled
1 = SATA Port 5 Dynamic Clock Gating is Enabled
17
SATA Port 4 Dynamic Clock Gate Enable — R/W.
0 = SATA Port 4 Dynamic Clock Gating is Disabled
1 = SATA Port 4 Dynamic Clock Gating is Enabled
16
PCI Dynamic Gate Enable — R/W.
0 = PCI Dynamic Gating is Disabled
1 = PCI Dynamic Gating is Enabled
15:6 Reserved
5
SMBus Clock Gating Enable (SMBCGEN) — R/W.
0 = SMBus Clock Gating is Disabled.
1 = SMBus Clock Gating is Enabled.
4:1 Reserved
0
PCI Express Root Port Static Clock Gate Enable — R/W.
0 = PCI Express root port Static Clock Gating is Disabled
1 = PCI Express root port Static Clock Gating is Enabled
Bit Description
Bit Description
7
Function Disable SUS Well Lockdown (FDSWL)— R/W03
0 = FDSW registers are not locked down
1 = FDSW registers are locked down
NOTE: This bit must be set when Intel
®
Active Management Technology is enabled.
6:0 Reserved