Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 408

Chipset Configuration Registers
408 Datasheet
10.1.77 DISPBDF—Display Bus, Device and Function Initialization
Offset Address: 3424–3425h Attribute: R/W
Default Value: 0010h Size: 16-bit
10.1.78 FD2—Function Disable 2
Offset Address: 3428–342Bh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
15:8
Display Bus Number (DBN) — R/W. The bus number of the Display in the
processor. BIOS should always program these bits as 0.
7:3
Display Device Number (DDN) — R/W. The device number of the Display in the
processor. BIOS should always program these bits as 2.
2:0
Display Function Number (DFN) — R/W. The function number of the Display in the
processor. BIOS should always program these bits as 0.
Bit Description
31:5 Reserved
4
KT Disable (KTD) —R/W. Default is 0.
0 = Keyboard Text controller (D22:F3) is enabled.
1 = Keyboard Text controller (D22:F3) is Disabled
3
IDE-R Disable (IRERD) —R/W. Default is 0.
0 = IDE Redirect controller (D22:F2) is Enabled.
1 = IDE Redirect controller (D22:F2) is Disabled.
2
Intel
®
MEI #2 Disable (MEI2D) —R/W. Default is 0.
0 = Intel
MEI controller #2 (D22:F1) is enabled.
1 = Intel
MEI controller #2 (D22:F1) is disabled.
1
Intel
MEI #1 Disable (MEI1D) —R/W. Default is 0.
0 = Intel
MEI controller #1 (D22:F0) is enabled.
1 = Intel
MEI controller #1 (D22:F0) is disabled.
0 Display BDF Enable (DBDFEN) —R/W.