Chipset Configuration Registers
410 Datasheet
10.1.80 USBOCM1—Overcurrent MAP Register 1
Offset Address: 35A0–35A3h Attribute: R/W0
Default Value: C0300C03h Size: 32-bit
All bits in this register are in the Resume Well and is only cleared by RSMRST#.
Bit Description
31:24
OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
23:16
OC2 Mapping Each bit position maps OC2# to a set of ports as follows: The OC2#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
15:8
OC1 Mapping Each bit position maps OC1# to a set of ports as follows: The OC1#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
7:0
OC0 Mapping Each bit position maps OC0# to a set of ports as follows: The OC0#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
Bit 31 30 29 28 27 26 25 24
Port 76543210
Bit 23 22 21 20 19 18 17 16
Port 76543210
Bit 15 14 13 12 11 10 9 8
Port 76543210
Bit 76543210
Port 76543210
To Next Page
Loading...