Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 411

Datasheet 411
Chipset Configuration Registers
10.1.81 USBOCM2—Overcurrent MAP Register 2
Offset Address: 35A4–35A7h Attribute: R/W0
Default Value: 00h Size: 32-bit
All bits in this register are in the Resume Well and is only cleared by RSMRST#
Bit Description
31:30 Reserved
29:24
OC7 Mapping Each bit position maps OC7# to a set of ports as follows: The OC7#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
23:22 Reserved
21:16
OC6 Mapping Each bit position maps OC6# to a set of ports as follows: The OC6#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
15:14 Reserved
13:8
OC5 Mapping Each bit position maps OC5# to a set of ports as follows: The OC5#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
7:6 Reserved
5:0
OC4 Mapping Each bit position maps OC4# to a set of ports as follows: The OC4#
pin is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
OC pin.
Bit 29 28 27 26 25 24
Port 13 12 11 10 9 8
Bit 21 20 19 18 17 16
Port 13 12 11 10 9 8
Bit 13 12 11 10 9 8
Port 13 12 11 10 9 8
Bit 543210
Port 13 12 11 10 9 8