Datasheet 419
PCI-to-PCI Bridge Registers (D30:F0)
11.1.5 RID—Revision Identification Register (PCI-PCI—D30:F0)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
11.1.6 CC—Class Code Register (PCI-PCI—D30:F0)
Offset Address: 09h–0Bh Attribute: RO
Default Value: 060401h Size: 24 bits
11
Signaled Target Abort (STA) — R/WC.
0 = No signaled target abort
1 = Set when the bridge generates a completion packet with target abort status on the
backbone.
10:9 Reserved.
8
Data Parity Error Detected (DPD) — R/WC.
0 = Data parity error Not detected.
1 = Set when the bridge receives a completion packet from the backbone from a
previous request, and detects a parity error, and CMD.PERE is set (D30:F0:04 bit 6).
7:5 Reserved.
4 Capabilities List (CLIST) — RO. Hardwired to 1. Capability list exist on the PCI bridge.
3
Interrupt Status (IS) — RO. Hardwired to 0. The PCI bridge does not generate
interrupts.
2:0 Reserved
Bit Description
Bit Description
7:0
Revision ID — RO. See the Intel
®
6 Series Chipset Specification Update for the value of
the RID Register.
Bit Description
23:16 Base Class Code (BCC) — RO. Hardwired to 06h. Indicates this is a bridge device.
15:8
Sub Class Code (SCC) — RO. Hardwired to 04h. Indicates this device is a PCI-to-PCI
bridge.
7:0
Programming Interface (PI) — RO. Hardwired to 01h. Indicates the bridge is
subtractive decode
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