PCI-to-PCI Bridge Registers (D30:F0)
420 Datasheet
11.1.7 PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
11.1.8 HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address: 0Eh Attribute: RO
Default Value: 01h Size: 8 bits
11.1.9 BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address: 18h–1Ah Attribute: R/W
Default Value: 000000h Size: 24 bits
Bit Description
7:3
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base
Specification, Revision 1.0a.
2:0 Reserved
Bit Description
7 Multi-Function Device (MFD) — RO. A 0 indicates a single function device
6:0
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the
configuration space, which is a PCI-to-PCI bridge in this case.
Bit Description
23:16
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number
below the bridge.
15:8 Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.
7:0
Primary Bus Number (PBN) — R/W. This field is default to 00h. In a multiple-PCH
system, programmable PBN allows an PCH to be located on any bus. System
configuration software is responsible for initializing these registers to appropriate
values. PBN is not used by hardware in determining its bus number.
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