Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Gigabit LAN Configuration Registers
440 Datasheet
12.1.16 CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0)
Address Offset: 34h Attribute: RO
Default Value: C8h Size: 8 bits
12.1.17 INTR—Interrupt Information Register
(Gigabit LAN—D25:F0)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: 0100h Size: 16 bits
Function Level Reset: No
12.1.18 MLMG—Maximum Latency/Minimum Grant Register
(Gigabit LAN—D25:F0)
Address Offset: 3Eh Attribute: RO
Default Value: 00h Size: 8 bits
12.1.19 CLIST 1—Capabilities List Register 1
(Gigabit LAN—D25:F0)
Address Offset: C8h–C9h Attribute: RO
Default Value: D001h Size: 16 bits
Bit Description
7:0
Capabilities Pointer (PTR) — RO. Indicates that the pointer for the first entry in the
capabilities list is at C8h in configuration space.
Bit Description
15:8
Interrupt Pin (IPIN) — RO. Indicates the interrupt pin driven by the GbE LAN
controller.
01h = The GbE LAN controller implements legacy interrupts on INTA.
7:0
Interrupt Line (ILINE) — R/W. Default = 00h. Software written value to indicate
which interrupt line (vector) the interrupt is connected to. No hardware action is taken
on this register.
Bit Description
7:0 Maximum Latency/Minimum Grant (MLMG) — RO. Not used. Hardwired to 00h.
Bit Description
15:8 Next Capability (NEXT) — RO. Value of D0h indicates the location of the next pointer.
7:0
Capability ID (CID) — RO. Indicates the linked list item is a PCI Power Management
Register.