Intel 6 SERIES CHIPSET - DATASHEET 01-2011

Datasheet 441
Gigabit LAN Configuration Registers
12.1.20 PMC—PCI Power Management Capabilities Register
(Gigabit LAN—D25:F0)
Address Offset: CAh–CBh Attribute: RO
Default Value: See bit descriptions Size: 16 bits
Function Level Reset: No (Bits 15:11 only)
Bit Description
15:11
PME_Support (PMES) — RO. This five-bit field indicates the power states in which the
function may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the
NVM:
These bits are not reset by Function Level Reset.
10 D2_Support (D2S) — RO. The D2 state is not supported.
9 D1_Support (D1S) — RO. The D1 state is not supported.
8:6 Aux_Current (AC) — RO. Required current defined in the Data Register.
5
Device Specific Initialization (DSI) — RO. Set to 1. The GbE LAN Controller requires
its device driver to be executed following transition to the D0 un-initialized state.
4 Reserved
3 PME Clock (PMEC) — RO. Hardwired to 0.
2:0
Version (VS) — RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI
Power Management Specification.
Condition Function Value
PM Ena=0 No PME at all states 0000b
PM Ena & AUX-PWR=0 PME at D0 and D3hot 01001b
PM Ena & AUX-PWR=1
PME at D0, D3hot and
D3cold
11001b