Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 451

Datasheet 451
LPC Interface Bridge Registers (D31:F0)
13.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah Attribute: RO
Default Value: 01h Size: 8 bits
13.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh Attribute: RO
Default Value: 06h Size: 8 bits
13.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
13.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh Attribute: RO
Default Value: 80h Size: 8 bits
Bit Description
7:0
Sub Class Code — RO. 8-bit value that indicates the category of bridge for the LPC
bridge.
01h = PCI-to-ISA bridge.
Bit Description
7:0
Base Class Code — RO. 8-bit value that indicates the type of device for the LPC
bridge.
06h = Bridge device.
Bit Description
7:3 Master Latency Count (MLC) — Reserved.
2:0 Reserved.
Bit Description
7 Multi-Function Device — RO. This bit is 1 to indicate a multi-function device.
6:0
Header Type — RO. This 7-bit field identifies the header layout of the configuration
space.