Datasheet 457
LPC Interface Bridge Registers (D31:F0)
13.1.18 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W
PIRQG
– 6Ah, PIRQH – 6Bh
Default Value: 80h Size: 8 bit
Lockable: No Power Well: Core
13.1.19 LPC_IBDF—IOxAPIC Bus:Device:Function
(LPC I/F—D31:F0)
Offset Address: 6Ch–6Dh Attribute: R/W
Default Value: 00F8h Size: 16 bit
Bit Description
7
Interrupt Routing Enable (IRQEN) — R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified
in bits[3:0].
1 = The PIRQ is not routed to the 8259.
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS when
setting up for I/O APIC interrupt delivery mode.
6:4 Reserved
3:0
IRQ Routing — R/W. (ISA compatible.)
Value IRQ Value IRQ
0000b Reserved 1000b Reserved
0001b Reserved 1001b IRQ9
0010b Reserved 1010b IRQ10
0011b IRQ3 1011b IRQ11
0100b IRQ4 1100b IRQ12
0101b IRQ5 1101b Reserved
0110b IRQ6 1110b IRQ14
0111b IRQ7 1111b IRQ15
Bit Description
15:0
IOxAPIC Bus:Device:Function (IBDF)— R/W. this field specifies the
bus:device:function that PCH’s IOxAPIC will be using for the following:
• As the Requester ID when initiating Interrupt Messages to the processor.
• As the Completer ID when responding to the reads targeting the IOxAPIC’s
Memory-Mapped I/O registers.
The 16-bit field comprises the following:
This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this
field to provide a unique bus:device:function number for the internal IOxAPIC.
Bits Description
15:8 Bus Number
7:3 Device Number
2:0 Function Number
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