Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 471

Datasheet 471
LPC Interface Bridge Registers (D31:F0)
13.1.36 FVECIDX—Feature Vector Index
(LPC I/F—D31:F0)
Offset Address: E4h–E7h Attribute: R/W
Default Value: 00000000h Size: 32 bit
Power Well: Core
13.1.37 FVECD—Feature Vector Data
(LPC I/F—D31:F0)
Offset Address: E8h–EBh Attribute: RO
Default Value: See Description Size: 32 bit
Power Well: Core
13.1.38 Feature Vector Space
13.1.38.1 FVEC0—Feature Vector Register 0
FVECIDX.IDX: 0000b Attribute: RO
Default Value: See Description Size: 32 bit
Power Well: Core
Bit Description
31:6 Reserved
5:2
Index (IDX) — R/W. 4-bit index pointer into the 64-byte Feature Vector space. Data
is read from the FVECD register. This points to a DWord register.
1:0 Reserved
Bit Description
31:0
Data (DATA) — RO. 32-bit data value that is read from the Feature Vector offset
pointed to by FVECIDX.
Bit Description
31:12 Reserved
11:10
USB Port Count Capability — RO
00 = 14 ports
01 = 12 ports
10 = 10 ports
11 = Reserved
9:8 Reserved
7
RAID Capability — RO
0 = Disabled
1 = Capable
6
SATA Ports 2 and 3 — RO
0 = Capable
1 = Disabled
5:4 Reserved