LPC Interface Bridge Registers (D31:F0)
480 Datasheet
13.2.8 DMA Clear Byte Pointer Register
I/O Address: Ch. #0–3 = 0Ch;
Ch. #4
–7 = D8h Attribute: WO
Default Value: xxxx xxxx Size: 8-bit
Lockable: No Power Well: Core
13.2.9 DMA Master Clear Register
I/O Address: Ch. #0–3 = 0Dh;
Ch. #4
–7 = DAh Attribute: WO
Default Value: xxxx xxxx Size: 8-bit
13.2.10 DMA_CLMSK—DMA Clear Mask Register
I/O Address: Ch. #0–3 = 0Eh;
Ch. #4
–7 = DCh Attribute: WO
Default Value: xxxx xxxx Size: 8-bit
Lockable: No Power Well: Core
Bit Description
7:0
Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the
I/O port address. Writing to this register initializes the byte pointer flip/flop to a known
state. It clears the internal latch used to address the upper or lower byte of the 16-bit
Address and Word Count Registers. The latch is also cleared by part reset and by the
Master Clear command. This command precedes the first access to a 16-bit DMA
controller register. The first access to a 16-bit register will then access the significant
byte, and the second access automatically accesses the most significant byte.
Bit Description
7:0
Master Clear — WO. No specific pattern. Enabled with a write to the port. This has the
same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer
flip/flop registers are cleared and the Mask Register is set.
Bit Description
7:0
Clear Mask Register — WO. No specific pattern. Command enabled with a write to the
port.
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