Datasheet 481
LPC Interface Bridge Registers (D31:F0)
13.2.11 DMA_WRMSK—DMA Write All Mask Register
I/O Address: Ch. #0–3 = 0Fh;
Ch. #4
–7 = DEh Attribute: R/W
Default Value: 0000 1111 Size: 8-bit
Lockable: No Power Well: Core
13.3 Timer I/O Registers
Bit Description
7:4 Reserved. Must be 0.
3:0
Channel Mask Bits — R/W. This register permits all four channels to be
simultaneously enabled/disabled instead of enabling/disabling each channel
individually, as is the case with the Mask Register – Write Single Mask Bit. In addition,
this register has a read path to allow the status of the channel mask bits to be read. A
channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register
reaches terminal count (unless the channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0
enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master
Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked
NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channels
0–3 through channel 4.
Port Aliases Register Name Default Value Type
40h 50h
Counter 0 Interval Time Status Byte Format 0XXXXXXXb RO
Counter 0 Counter Access Port Undefined R/W
41h 51h
Counter 1 Interval Time Status Byte Format 0XXXXXXXb RO
Counter 1 Counter Access Port Undefined R/W
42h 52h
Counter 2 Interval Time Status Byte Format 0XXXXXXXb RO
Counter 2 Counter Access Port Undefined R/W
43h 53h
Timer Control Word Undefined WO
Timer Control Word Register XXXXXXX0b WO
Counter Latch Command X0h WO
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