Intel 6 SERIES CHIPSET - DATASHEET 01-2011 User Manual

LPC Interface Bridge Registers (D31:F0)
492 Datasheet
13.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
Offset Address: 4D1h Attribute: R/W
Default Value: 00h Size: 8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Bit Description
7
IRQ15 ECL — R/W.
0 = Edge
1 = Level
6
IRQ14 ECL — R/W.
0 = Edge
1 = Level
5 Reserved. Must be 0.
4
IRQ12 ECL — R/W.
0 = Edge
1 = Level
3
IRQ11 ECL — R/W.
0 = Edge
1 = Level
2
IRQ10 ECL — R/W.
0 = Edge
1 = Level
1
IRQ9 ECL — R/W.
0 = Edge
1 = Level
0 Reserved. Must be 0.

Intel 6 SERIES CHIPSET - DATASHEET 01-2011 Specifications

General

Brand	Intel
Model	6 SERIES CHIPSET - DATASHEET 01-2011
Category	Controller
Language	English