Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 603

Datasheet 603
SATA Controller Registers (D31:F2)
14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)
Address Offset: Port 0: ABAR + 108h Attribute: R/W
Port 1: ABAR + 188h
Port 2: ABAR + 208h (if port available; see Section 1.3)
Port 3: ABAR + 288h (if port available; see Section 1.3)
Port 4: ABAR + 308h
Port 5: ABAR + 388h
Default Value: Undefined Size: 32 bits
14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
Register (D31:F2)
Address Offset: Port 0: ABAR + 10Ch Attribute: R/W
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch (if port available; see Section 1.3)
Port 3: ABAR + 28Ch (if port available; see Section 1.3)
Port 4: ABAR + 30Ch
Port 5: ABAR + 38Ch
Default Value: Undefined Size: 32 bits
Bit Description
31:8
FIS Base Address (FB) — R/W. Indicates the 32-bit base for received FISes. The
structure pointed to by this address range is 256 bytes in length. This address must be
256-byte aligned, as indicated by bits 31:3 being read/write.
Note that these bits are not reset on a Controller reset.
7:0 Reserved
Bit Description
31:0
Command List Base Address Upper (CLBU) — R/W. Indicates the upper 32-bits for
the received FIS base for this port.
Note that these bits are not reset on a Controller reset.