SATA Controller Registers (D31:F2)
604 Datasheet
14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2)
Address Offset: Port 0: ABAR + 110h Attribute: R/WC, RO
Port 1: ABAR + 190h
Port 2: ABAR + 210h (if port available; see Section 1.3)
Port 3: ABAR + 290h (if port available; see Section 1.3)
Port 4: ABAR + 310h
Port 5: ABAR + 390h
Default Value: 00000000h Size: 32 bits
Bit Description
31 Cold Port Detect Status (CPDS) — RO. Cold presence detect is not supported.
30
Task File Error Status (TFES) — R/WC. This bit is set whenever the status register is
updated by the device and the error bit (PxTFD.bit 0) is set.
29
Host Bus Fatal Error Status (HBFS) — R/WC. Indicates that the PCH encountered an
error that it cannot recover from due to a bad software pointer. In PCI, such an
indication would be a target or master abort.
28
Host Bus Data Error Status (HBDS) — R/WC. Indicates that the PCH encountered a
data error (uncorrectable ECC / parity) when reading from or writing to system memory.
27
Interface Fatal Error Status (IFS) — R/WC. Indicates that the PCH encountered an
error on the SATA interface which caused the transfer to stop.
26
Interface Non-fatal Error Status (INFS) — R/WC. Indicates that the PCH
encountered an error on the SATA interface but was able to continue operation.
25 Reserved
24
Overflow Status (OFS) — R/WC. Indicates that the PCH received more bytes from a
device than was specified in the PRD table for the command.
23
Incorrect Port Multiplier Status (IPMS) — R/WC. Indicates that the PCH received a
FIS from a device whose Port Multiplier field did not match what was expected.
NOTE: FIS based Port Multipliers are not supported by the PCH.
22
PhyRdy Change Status (PRCS) — RO. When set to one, this bit indicates the internal
PhyRdy signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most
of the other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is
cleared.
Note that the internal PhyRdy signal also transitions when the port interface enters
partial or slumber power management states. Partial and slumber must be disabled
when Surprise Removal Notification is desired, otherwise the power management state
transitions will appear as false insertion and removal events.
21:8 Reserved
7
Device Interlock Status (DIS) — R/WC. When set, this bit indicates that a platform
mechanical presence switch has been opened or closed, which may lead to a change in
the connection state of the device. This bit is only valid in systems that support an
mechanical presence switch (CAP.SIS [ABAR+00:bit 28] set).
For systems that do not support an mechanical presence switch, this bit will always be
0.
6
Port Connect Change Status (PCS) — RO. This bit reflects the state of
PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this
register, this bit is only cleared when PxSERR.DIAG.X is cleared.
0 = No change in Current Connect Status.
1 = Change in Current Connect Status.
5
Descriptor Processed (DPS) — R/WC. A PRD with the I bit set has transferred all its
data.
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