Datasheet 605
SATA Controller Registers (D31:F2)
14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2)
Address Offset: Port 0: ABAR + 114h Attribute: R/W, RO
Port 1: ABAR + 194h
Port 2: ABAR + 214h (if port available; see Section 1.3)
Port 3: ABAR + 294h (if port available; see Section 1.3)
Port 4: ABAR + 314h
Port 5: ABAR + 394h
Default Value: 00000000h Size: 32 bits
This register enables and disables the reporting of the corresponding interrupt to
system software. When a bit is set (1) and the corresponding interrupt condition is
active, then an interrupt is generated. Interrupt sources that are disabled (0) are still
reflected in the status registers.
4
Unknown FIS Interrupt (UFS) — RO. When set to 1, this bit indicates that an
unknown FIS was received and has been copied into system memory. This bit is cleared
to 0 by software clearing the PxSERR.DIAG.F bit to 0. Note that this bit does not directly
reflect the PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown FIS
is detected, whereas this bit is set when the FIS is posted to memory. Software should
wait to act on an unknown FIS until this bit is set to 1 or the two bits may become out of
sync.
3
Set Device Bits Interrupt (SDBS) — R/WC. A Set Device Bits FIS has been received
with the I bit set and has been copied into system memory.
2
DMA Setup FIS Interrupt (DSS) — R/WC. A DMA Setup FIS has been received with
the I bit set and has been copied into system memory.
1
PIO Setup FIS Interrupt (PSS) — R/WC. A PIO Setup FIS has been received with the
I bit set, it has been copied into system memory, and the data related to that FIS has
been transferred.
0
Device to Host Register FIS Interrupt (DHRS) — R/WC. A D2H Register FIS has
been received with the I bit set, and has been copied into system memory.
Bit Description
Bit Description
31 Cold Presence Detect Enable (CPDE) — RO. Cold Presence Detect is not supported.
30
Task File Error Enable (TFEE) — R/W. When set, and GHC.IE and PxTFD.STS.ERR
(due to a reception of the error register from a received FIS) are set, the PCH will
generate an interrupt.
29
Host Bus Fatal Error Enable (HBFE) — R/W. When set, and GHC.IE and PxS.HBFS
are set, the PCH will generate an interrupt.
28
Host Bus Data Error Enable (HBDE) — R/W. When set, and GHC.IE and PxS.HBDS
are set, the PCH will generate an interrupt.
27
Host Bus Data Error Enable (HBDE) — R/W. When set, GHC.IE is set, and
PxIS.HBDS is set, the PCH will generate an interrupt.
26
Interface Non-fatal Error Enable (INFE) — R/W. When set, GHC.IE is set, and
PxIS.INFS is set, the PCH will generate an interrupt.
25 Reserved
24
Overflow Error Enable (OFE) — R/W. When set, and GHC.IE and PxS.OFS are set,
the PCH will generate an interrupt.
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