SATA Controller Registers (D31:F2)
606 Datasheet
23
Incorrect Port Multiplier Enable (IPME) — R/W. When set, and GHC.IE and
PxIS.IPMS are set, the PCH will generate an interrupt.
NOTE: FIS based Port Multipliers only supported on SATA ports 4 and 5 by PCH
22
PhyRdy Change Interrupt Enable (PRCE) — R/W. When set, and GHC.IE is set, and
PxIS.PRCS is set, the PCH shall generate an interrupt.
21:8 Reserved
7
Device Interlock Enable (DIE) — R/W. When set, and PxIS.DIS is set, the PCH will
generate an interrupt.
For systems that do not support an mechanical presence switch, this bit shall be a read-
only 0.
6
Port Change Interrupt Enable (PCE) — R/W. When set, and GHC.IE and PxS.PCS
are set, the PCH will generate an interrupt.
5
Descriptor Processed Interrupt Enable (DPE) — R/W. When set, and GHC.IE and
PxS.DPS are set, the PCH will generate an interrupt.
4
Unknown FIS Interrupt Enable (UFIE) — R/W. When set, and GHC.IE is set and an
unknown FIS is received, the PCH will generate this interrupt.
3
Set Device Bits FIS Interrupt Enable (SDBE) — R/W. When set, and GHC.IE and
PxS.SDBS are set, the PCH will generate an interrupt.
2
DMA Setup FIS Interrupt Enable (DSE) — R/W. When set, and GHC.IE and PxS.DSS
are set, the PCH will generate an interrupt.
1
PIO Setup FIS Interrupt Enable (PSE) — R/W. When set, and GHC.IE and PxS.PSS
are set, the PCH will generate an interrupt.
0
Device to Host Register FIS Interrupt Enable (DHRE) — R/W. When set, and
GHC.IE and PxS.DHRS are set, the PCH will generate an interrupt.
Bit Description
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