Datasheet 607
SATA Controller Registers (D31:F2)
14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2)
Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO
Port 1: ABAR + 198h
Port 2: ABAR + 218h (if port available; see Section 1.3)
Port 3: ABAR + 298h (if port available; see Section 1.3)
Port 4: ABAR + 318h
Port 5: ABAR + 398h
Default Value: 0000w00wh Size: 32 bits
where w = 00?0b (for?, see bit description)
Function Level Reset:No (Bit 21, 19 and 18 only)
Bit Description
31:28
Interface Communication Control (ICC) — R/W.This is a four bit field that can be
used to control reset and power states of the interface. Writes to this field will cause
actions on the interface, either as primitives or an OOB sequence, and the resulting
status of the interface will be reported in the PxSSTS register (Address offset Port
0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h, Port 4:
ABAR+224h, Port 5: ABAR+2A4h).
When system software writes a non-reserved value other than No-Op (0h), the PCH
will perform the action and update this field back to Idle (0h).
If software writes to this field to change the state to a state the link is already in
(such as, interface is in the active state and a request is made to go to the active
state), the PCH will take no action and return this field to Idle.
NOTE: When the ALPE bit (bit 26) is set, then this register should not be set to 02h
or 06h.
27
Aggressive Slumber / Partial (ASP) — R/W. When set to 1, and the ALPE bit (bit
26) is set, the PCH shall aggressively enter the slumber state when it clears the PxCI
register and the PxSACT register is cleared. When cleared, and the ALPE bit is set, the
PCH will aggressively enter the partial state when it clears the PxCI register and the
PxSACT register is cleared. If CAP.SALP is cleared to 0, software shall treat this bit as
reserved.
26
Aggressive Link Power Management Enable (ALPE) — R/W. When set to 1, the
PCH will aggressively enter a lower link power state (partial or slumber) based upon
the setting of the ASP bit (bit 27).
Value Definition
Fh–7h Reserved
6h
Slumber: This will cause the PCH to request a transition of the
interface to the slumber state. The SATA device may reject the
request and the interface will remain in its current state
5h–3h Reserved
2h
Partial: This will cause the PCH to request a transition of the
interface to the partial state. The SATA device may reject the
request and the interface will remain in its current state.
1h
Active: This will cause the PCH to request a transition of the
interface into the active
0h
No-Op / Idle: When software reads this value, it indicates the PCH is
not in the process of changing the interface state or sending a
device reset, and a new link command may be issued.
To Next Page
Loading...
