Datasheet 619
SATA Controller Registers (D31:F5)
15.1.3 PCICMD—PCI Command Register (SATA–D31:F5)
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
10
Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
enabled.
1 = Internal INTx# messages will not be generated.
9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.
8 SERR# Enable (SERR_EN) — RO. Reserved as 0.
7 Wait Cycle Control (WCC) — RO. Reserved as 0.
6
Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is
detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
5 VGA Palette Snoop (VPS) — RO. Reserved as 0.
4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
3 Special Cycle Enable (SCE) — RO. Reserved as 0.
2
Bus Master Enable (BME) — R/W. This bit controls the
PCH ability to act as a PCI
master for IDE Bus Master transfers. This bit does not impact the generation of
completions for split transaction commands.
1
Memory Space Enable (MSE) — RO. This controller does not support AHCI;
therefore, no memory space is required.
0
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as
well as the Bus Master I/O registers.
1 = Enable. Note that the Base Address register for the Bus Master registers should be
programmed before this bit is set.
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