Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 622

SATA Controller Registers (D31:F5)
622 Datasheet
15.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F5)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
15.1.10 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
15.1.11 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F5)
Address Offset: 14h–17h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
Bit Description
7:0
Master Latency Timer Count (MLTC) — RO.
00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated
as a PCI device, so it does not need a Master Latency Timer.
Bit Description
31:16 Reserved
15:3
Base Address — R/W. This field provides the base address of the I/O space (8
consecutive I/O locations).
2:1 Reserved
0
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.
Bit Description
31:16 Reserved
15:2
Base Address — R/W. This field provides the base address of the I/O space (4
consecutive I/O locations).
1 Reserved
0
Resource Type Indicator (RTE) — RO. Hardwired to 1 to indicate a request for I/O
space.