SATA Controller Registers (D31:F5)
626 Datasheet
15.1.21 IDE_TIM — IDE Timing Register (SATA–D31:F5)
Address Offset: Primary: 40h–41h Attribute: R/W
Secondary: 42h–43h
Default Value: 0000h Size: 16 bits
15.1.22 PID—PCI Power Management Capability Identification
Register (SATA–D31:F5)
Address Offset: 70h–71h Attribute: RO
Default Value: B001h Size: 16 bits
15.1.23 PC—PCI Power Management Capabilities Register
(SATA–D31:F5)
Address Offset: 72h–73h Attribute: RO
Default Value: 4003h Size: 16 bits
f
Bit Description
15
IDE Decode Enable (IDE) — R/W. Individually enable/disable the Primary or
Secondary decode.
0 = Disable.
1 = Enables the PCH to decode the associated Command Blocks (1F0–1F7h for primary,
170–177h for secondary) and Control Block (3F6h for primary and 376h for
secondary).
This bit effects the IDE decode ranges for both legacy and native-Mode decoding.
NOTE: This bit affects SATA operation in both combined and non-combined ATA modes.
See Section 5.16 for more on ATA modes of operation.
14:0 Reserved
Bits Description
15:8
Next Capability (NEXT) — RO. When SCC is 01h, this field will be B0h indicating the
next item is FLR Capability Pointer in the list.
7:0 Capability ID (CID) — RO. Indicates that this pointer is a PCI power management.
Bits Description
15:11
PME Support (PME_SUP) — RO. By default with SCC = 01h, the default value of
00000 indicates no PME support in IDE mode.
10 D2 Support (D2_SUP) — RO. Hardwired to 0. The D2 state is not supported
9 D1 Support (D1_SUP) — RO. Hardwired to 0. The D1 state is not supported
8:6
Auxiliary Current (AUX_CUR) — RO. PME# from D3
COLD
state is not supported,
therefore this field is 000b.
5
Device Specific Initialization (DSI) — RO. Hardwired to 0 to indicate that no device-
specific initialization is required.
4 Reserved
3
PME Clock (PME_CLK) — RO. Hardwired to 0 to indicate that PCI clock is not required to
generate PME#.
2:0
Version (VER) — RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI
Power Management Specification.
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