Datasheet 627
SATA Controller Registers (D31:F5)
15.1.24 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F5)
Address Offset: 74h–75h Attribute: RO, R/W, R/WC
Default Value: 0008h Size: 16 bits
Function Level Reset:No (Bits 8 and 15 only)
Bits Description
15
PME Status (PMES) — R/WC. Bit is set when a PME event is to be requested, and if
this bit and PMEE is set, a PME# will be generated from the SATA controller.
NOTE: When SCC=01h this bit will be RO 0. Software is advised to clear PMEE together
with PMES prior to changing SCC through MAP.SMS.
This bit is not reset by Function Level Reset.
14:9 Reserved
8
PME Enable (PMEE) — R/W. When SCC is not 01h, this bit R/W. When set, the SATA
controller generates PME# form D3
HOT
on a wake event.
Note: When SCC=01h this bit will be RO 0. Software is advised to clear PMEE together
with PMES prior to changing SCC through MAP.SMS.
This bit is not reset by Function Level Reset.
7:4 Reserved
3
No Soft Reset (NSFRST) — RO. These bits are used to indicate whether devices
transitioning from D3
HOT
state to D0 state will perform an internal reset.
0 = Device transitioning from D3
HOT
state to D0 state perform an internal reset.
1 = Device transitioning from D3
HOT
state to D0 state do not perform an internal reset.
Configuration content is preserved. Upon transition from the D3
HOT
state to D0 state
initialized state, no additional operating system intervention is required to preserve
configuration context beyond writing to the PowerState bits.
Regardless of this bit, the controller transition from D3
HOT
state to D0 state by a system
or bus segment reset will return to the state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
2Reserved
1:0
Power State (PS) — R/W. These bits are used both to determine the current power
state of the
SATA controller and to set a new power state.
00 = D0 state
11 = D3
HOT
state
When in the D3
HOT
state, the controller’s configuration space is available, but the I/O
and memory spaces are not. Additionally, interrupts are blocked.
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