Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 644

EHCI Controller Registers (D29:F0, D26:F0)
644 Datasheet
16.1.4 PCISTS—PCI Status Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0290h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
15
Detected Parity Error (DPE) — R/WC.
0 = No parity error detected.
1 = This bit is set by the PCH when a parity error is seen by the EHCI controller,
regardless of the setting of bit 6 or bit 8 in the Command register or any other
conditions.
14
Signaled System Error (SSE) — R/WC.
0 = No SERR# signaled by the PCH.
1 = This bit is set by the PCH when it signals SERR# (internally). The SER_EN bit (bit 8
of the Command Register) must be 1 for this bit to be set.
13
Received Master Abort (RMA) — R/WC.
0 = No master abort received by EHC on a memory access.
1 = This bit is set when EHC, as a master, receives a master abort status on a memory
access. This is treated as a Host Error and halts the DMA engines. This event can
optionally generate an SERR# by setting the SERR# Enable bit
.
12
Received Target Abort (RTA) — R/WC.
0 = No target abort received by EHC on memory access.
1 = This bit is set when EHC, as a master, receives a target abort status on a memory
access. This is treated as a Host Error and halts the DMA engines. This event can
optionally generate an SERR# by setting the SERR# Enable bit (D29:F0,
D26:F0:04h, bit 8).
11
Signaled Target Abort (STA) — RO. This bit is used to indicate when the EHCI function
responds to a cycle with a target abort. There is no reason for this to happen, so this bit
is hardwired to 0.
10:9
DEVSEL# Timing Status (DEVT_STS) — RO. This 2-bit field defines the timing for
DEVSEL# assertion.
8
Master Data Parity Error Detected (DPED) — R/WC.
0 = No data parity error detected on USB2.0 read completion packet.
1 = This bit is set by the PCH when a data parity error is detected on a USB 2.0 read
completion packet on the internal interface to the EHCI host controller and bit 6 of
the Command register is set to 1.
7 Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
6 User Definable Features (UDF) — RO. Hardwired to 0.
5 66 MHz Capable (66 MHz _CAP) — RO. Hardwired to 0.
4
Capabilities List (CAP_LIST) — RO. Hardwired to 1 indicating that offset 34h contains a
valid capabilities pointer.
3
Interrupt Status — RO. This bit reflects the state of this function’s interrupt at the
input of the enable/disable logic.
0 = This bit will be 0 when the interrupt is deasserted.
1 = This bit is a 1 when the interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
2:0 Reserved