Datasheet 643
EHCI Controller Registers (D29:F0, D26:F0)
16.1.3 PCICMD—PCI Command Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
10
Interrupt Disable — R/W.
0 = The function is capable of generating interrupts.
1 = The function can not generate its interrupt to the interrupt controller.
Note that the corresponding Interrupt Status bit (D29:F0, D26:F0:06h, bit 3) is not
affected by the interrupt enable.
9 Fast Back to Back Enable (FBE) — RO. Hardwired to 0.
8
SERR# Enable (SERR_EN) — R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR# in
the following cases:
• When it receive a completion status other than “successful” for one of its DMA initiated
memory reads on DMI (and subsequently on its internal interface).
• When it detects an address or command parity error and the Parity Error Response bit is
set.
• When it detects a data parity error (when the data is going into the EHC) and the Parity
Error Response bit is set.
7 Wait Cycle Control (WCC) — RO. Hardwired to 0.
6
Parity Error Response (PER) — R/W.
0 = The EHC is not checking for correct parity (on its internal interface).
1 = The EHC is checking for correct parity (on its internal interface) and halt operation
when bad parity is detected during the data phase.
NOTE: If the EHC detects bad parity on the address or command phases when the bit is
set to 1, the host controller does not take the cycle. It halts the host controller
(if currently not halted) and sets the Host System Error bit in the USBSTS
register. This applies to both requests and completions from the system
interface.
This bit must be set in order for the parity errors to generate SERR#.
5 VGA Palette Snoop (VPS) — RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE) — RO. Hardwired to 0.
3 Special Cycle Enable (SCE) — RO. Hardwired to 0.
2
Bus Master Enable (BME) — R/W.
0 = Disables this functionality.
1 = Enables the PCH to act as a master on the PCI bus for USB transfers.
1
Memory Space Enable (MSE) — R/W. This bit controls access to the USB 2.0 Memory
Space registers.
0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F0,
D26:F0:10h) for USB 2.0 should be programmed before this bit is set.
0 I/O Space Enable (IOSE) — RO. Hardwired to 0.
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