Datasheet 65
Signal Description
SLP_LAN# /
GPIO29
O
LAN Sub-System Sleep Control: When SLP_LAN# is deasserted
it indicates that the PHY device must be powered. When SLP_LAN#
is asserted, power can be shut off to the PHY device. SLP_LAN#
will always be deasserted in S0 and anytime SLP_A# is deasserted.
SLP_LAN# behavior in Sx/Moff can be configured by Intel ME FW.
When SLP_LAN#/GPIO Select Soft-strap is set to SLP_LAN#
operation and If neither Intel ME FW nor host BIOS configures
SLP_LAN#, its behavior will be based on the setting of the RTC
backed SLP_LAN# Default Bit (D31:F0:A4h:bit 8).
NOTES:
1. The SLP_LAN# Default Value Bit will always determine
SLP_LAN# behavior when in S4/S5/Moff after a G3, when
in S5/Moff after a host partition reset with power down and
when in S5/Moff due to an unconditional power down.
2. A SLP_LAN#/GPIO Select Soft-Strap can be used for
systems NOT using SLP_LAN# functionality to revert to
GPIO29 usage. When soft-strap is 0 (default), pin function
will be SLP_LAN#. When soft-strap is set to 1, the pin
returns to its regular GPIO mode.
SLP_S3# O
S3 Sleep Control: SLP_S3# is for power plane control. This signal
shuts off power to all non-critical systems when in S3 (Suspend To
RAM), S4 (Suspend to Disk), or S5 (Soft Off) states.
SLP_S4# O
S4 Sleep Control: SLP_S4# is for power plane control. This signal
shuts power to all non-critical systems when in the S4 (Suspend to
Disk) or S5 (Soft Off) state.
NOTE: This pin must be used to control the DRAM power in order
to use the PCH’s DRAM power-cycling feature. Refer to
Chapter 5.13.10.2 for details
SLP_S5# /
GPIO63
O
S5 Sleep Control: SLP_S5# is for power plane control. This signal
is used to shut power off to all non-critical systems when in the S5
(Soft Off) states.
Pin may also be used as GPIO63.
SLP_SUS# O
Deep S4/S5 Indication: When asserted low, this signal indicates
PCH is in Deep S4/S5 state where internal Sus power is shut off for
enhanced power saving. If Deep S4/S5 is not supported, then this
pin can be left unconnected.
This pin is in the DSW power well.
STP_PCI# /
GPIO34
O
Stop PCI Clock: This signal is an output to the clock generator for
it to turn off the PCI clock.
SUSACK# I
SUSACK#: If Deep S4/S5 is supported, the EC/motherboard
controlling logic must change SUSACK# to match SUSWARN# once
the EC/motherboard controlling logic has completed the
preparations discussed in the description for the SUSWARN# pin.
NOTE: SUSACK# is only required to change in response to
SUSWARN# if Deep S4/S5 is supported by the platform.
This pin is in the Sus power well.
Table 2-8. Power Management Interface Signals (Sheet 3 of 4)
Name Type Description
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