EHCI Controller Registers (D29:F0, D26:F0)
652 Datasheet
16.1.25 FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 61h Attribute: R/W
Default Value: 20h Size: 8 bits
Function Level Reset: No
This feature is used to adjust any offset from the clock source that generates the clock
that drives the SOF counter. When a new value is written into these six bits, the length
of the frame is adjusted. Its initial programmed value is system dependent based on
the accuracy of hardware USB clock and is initialized by system BIOS. This register
should only be modified when the HChalted bit (D29:F0, D26:F0:CAPLENGTH + 24h,
bit 12) in the USB2.0_STS register is a 1. Changing value of this register while the host
controller is operating yields undefined results. It should not be reprogrammed by USB
system software unless the default or BIOS programmed values are incorrect, or the
system is restoring the register while returning from a suspended state.
These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
7:6 Reserved — RO. These bits are reserved for future use and should read as 00b.
5:0
Frame Length Timing Value — R/W. Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter
clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this
field. The default value is decimal 32 (20h) that gives a SOF cycle time of 60000.
Frame Length (# 480 MHz
Clocks) (decimal)
Frame Length Timing Value (this
register) (decimal)
59488 0
59504 1
59520 2
——
59984 31
60000 32
——
60480 62
To Next Page
Loading...