Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 651

Datasheet 651
EHCI Controller Registers (D29:F0, D26:F0)
16.1.21 DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 58h Attribute: RO
Default Value: 0Ah Size: 8 bits
16.1.22 NXT_PTR2—Next Item Pointer #2 Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 59h Attribute: RO
Default Value: 98h Size: 8 bits
Function Level Reset: No
16.1.23 DEBUG_BASE—Debug Port Base Offset Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 5Ah–5Bh Attribute: RO
Default Value: 20A0h Size: 16 bits
16.1.24 USB_RELNUM—USB Release Number Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 60h Attribute: RO
Default Value: 20h Size: 8 bits
Bit Description
7:0
Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a
Debug Port Capability structure.
Bit Description
7:0
Next Item Pointer 2 Capability — RO. This register points to the next capability in
the Function Level Reset capability structure.
Bit Description
15:13
BAR Number — RO. Hardwired to 001b to indicate the memory BAR begins at offset
10h in the EHCI configuration space.
12:0
Debug Port Offset — RO. Hardwired to 0A0h to indicate that the Debug Port registers
begin at offset A0h in the EHCI memory range.
Bit Description
7:0
USB Release Number — RO. A value of 20h indicates that this controller follows
Universal Serial Bus (USB) Specification, Revision 2.0.