Intel 6 SERIES CHIPSET - DATASHEET 01-2011 - Page 655

Datasheet 655
EHCI Controller Registers (D29:F0, D26:F0)
16.1.28 LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 6C–6Fh Attribute: R/W, R/WC, RO
Default Value: 00000000h Size: 32 bits
Power Well: Suspend
Function Level Reset: No
Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
31
SMI on BAR — R/WC. Software clears this bit by writing a 1 to it.
0 = Base Address Register (BAR) not written.
1 = This bit is set to 1 when the Base Address Register (BAR) is written.
30
SMI on PCI Command — R/WC. Software clears this bit by writing a 1 to it.
0 = PCI Command (PCICMD) Register Not written.
1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written.
29
SMI on OS Ownership Change — R/WC. Software clears this bit by writing a 1 to it.
0 = No HC OS Owned Semaphore bit change.
1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP
register (D29:F0, D26:F0:68h, bit 24) transitions from 1 to 0 or 0 to 1.
28:22 Reserved.
21
SMI on Async Advance — RO. This bit is a shadow bit of the Interrupt on Async
Advance bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Interrupt on Async
Advance bit in the USB2.0_STS register.
20
SMI on Host System Error — RO. This bit is a shadow bit of Host System Error bit in
the USB2.0_STS register (D29:F0, D26:F0:CAPLENGTH + 24h, bit 4).
NOTE: To clear this bit system software must write a 1 to the Host System Error bit in
the USB2.0_STS register.
19
SMI on Frame List Rollover — RO. This bit is a shadow bit of Frame List Rollover bit
(D29:F0, D26:F0:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in
the USB2.0_STS register.
18
SMI on Port Change Detect — RO. This bit is a shadow bit of Port Change Detect bit
(D29:F0, D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in
the USB2.0_STS register.
17
SMI on USB Error — RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT)
bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in
the USB2.0_STS register.
16
SMI on USB Complete — RO. This bit is a shadow bit of USB Interrupt (USBINT) bit
(D29:F0, D26:F0:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register.
NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the
USB2.0_STS register.